From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?windows-1252?Q?Roger_Pau_Monn=E9?= Subject: Re: [PATCH v3 10/10] x86/MSI-X: provide hypercall interface for mask-all control Date: Mon, 22 Jun 2015 19:02:02 +0200 Message-ID: <55883F8A.20304@citrix.com> References: <55719F9D0200007800081425@mail.emea.novell.com> <5571A3F202000078000814CA@mail.emea.novell.com> <557964870200007800083706@mail.emea.novell.com> <55795A3D.7060304@citrix.com> <55842E9702000078000870C9@mail.emea.novell.com> <5584222F.90707@citrix.com> <55844A39020000780008717F@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z757K-0005hY-9o for xen-devel@lists.xenproject.org; Mon, 22 Jun 2015 17:02:42 +0000 In-Reply-To: <55844A39020000780008717F@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Wei Liu , Stefano Stabellini , Andrew Cooper , Ian Jackson , Ian Campbell , xen-devel , dgdegra@tycho.nsa.gov, Keir Fraser List-Id: xen-devel@lists.xenproject.org El 19/06/15 a les 16.58, Jan Beulich ha escrit: >>>> On 19.06.15 at 16:07, wrote: >> I don't mind adding a PHYSDEVOP_pci_mmcfg_reserved call to FreeBSD, but >> for it to have any effect we need to stop unconditionally mapping >> everything as MMIO regions on PVH Dom0. > > Right, I didn't mean to imply PVH would have any chance of working > right now. > > But what you didn't respond to is the (kind of implicit I admit) question > of whether FreeBSD is using MMCFG accesses for the low 256 bytes > of the config space. (I note that there's one special case in Linux - > NumaChip - whether this is the case.) OK, I didn't get the part of the question. AFAICT yes, FreeBSD will access the low 256 bytes of the config space. For example the stub to write to a cfg register is as follows: void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { if (cfgmech == CFGMECH_PCIE && (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else pcireg_cfgwrite(bus, slot, func, reg, data, bytes); } I take that you would prefer it to be: void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { if (cfgmech == CFGMECH_PCIE && (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots)) && (reg > PCI_REGMAX)) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else pcireg_cfgwrite(bus, slot, func, reg, data, bytes); } Where 'PCI_REGMAX' is 255. Roger.