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From: weigelt@melag.de (Enrico Weigelt, metux IT consult)
To: linux-arm-kernel@lists.infradead.org
Subject: L2 Cache enable on i.MX5
Date: Thu, 25 Jun 2015 10:37:41 +0200	[thread overview]
Message-ID: <558BBDD5.3020306@melag.de> (raw)
In-Reply-To: <DBXPR06MB58911B5FD193722EC5BD34185AF0@DBXPR06MB589.eurprd06.prod.outlook.com>

Am 25.06.2015 um 00:53 schrieb Robert Daniels:

Hi,


> In that case, where should the kernel be enabling the L2 cache? I'm using the
> 3.14 kernel for this i.MX53 product and the L2 cache is definitely not enabled.

I'm working on an mx53, too (tqma53 board), but with an 4.1 kernel.
How can I check whether L2 cache is enabled ?

Can you estimate, how much performance gain we can actually get from the
L2 cache (under which kind of workloads) ?


--mtx

--
Enrico Weigelt, metux IT consult
+49-151-27565287
MELAG Medizintechnik oHG Sitz Berlin Registergericht AG Charlottenburg HRA 21333 B

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  parent reply	other threads:[~2015-06-25  8:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-24 17:10 L2 Cache enable on i.MX5 Robert Daniels
2015-06-24 17:29 ` Russell King - ARM Linux
2015-06-24 22:53   ` Robert Daniels
2015-06-24 23:13     ` Russell King - ARM Linux
2015-06-25  8:37     ` Enrico Weigelt, metux IT consult [this message]
2015-06-25 16:15       ` Robert Daniels
2015-06-25 21:29     ` Fabio Estevam

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