From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z89ZR-0002K5-Q7 for qemu-devel@nongnu.org; Thu, 25 Jun 2015 12:00:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z89ZN-0003Aa-IC for qemu-devel@nongnu.org; Thu, 25 Jun 2015 12:00:09 -0400 Received: from cantor2.suse.de ([195.135.220.15]:55390 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z89ZN-00038E-7J for qemu-devel@nongnu.org; Thu, 25 Jun 2015 12:00:05 -0400 Message-ID: <558C2583.1040501@suse.de> Date: Thu, 25 Jun 2015 18:00:03 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <4b8fc4d985de6c4f44509b9c47a6152add36d832.1435195913.git.zhugh.fnst@cn.fujitsu.com> In-Reply-To: <4b8fc4d985de6c4f44509b9c47a6152add36d832.1435195913.git.zhugh.fnst@cn.fujitsu.com> Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RESEND PATCH v8 1/4] apic: map APIC's MMIO region at each CPU's address space List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Zhu Guihua , qemu-devel@nongnu.org, pbonzini@redhat.com, ehabkost@redhat.com Cc: chen.fan.fnst@cn.fujitsu.com, imammedo@redhat.com, izumi.taku@jp.fujitsu.com Am 25.06.2015 um 04:17 schrieb Zhu Guihua: > From: Chen Fan >=20 > Replace mapping APIC at global system address space with > mapping it at per-CPU address spaces. >=20 > Signed-off-by: Chen Fan > Signed-off-by: Zhu Guihua > --- > exec.c | 5 +++++ > hw/i386/pc.c | 7 ------- > hw/intc/apic_common.c | 14 ++++++++------ > include/exec/memory.h | 5 +++++ > target-i386/cpu.c | 2 ++ > 5 files changed, 20 insertions(+), 13 deletions(-) Eduardo, is this for you? > diff --git a/exec.c b/exec.c > index f7883d2..1cd2e74 100644 > --- a/exec.c > +++ b/exec.c > @@ -2710,6 +2710,11 @@ void address_space_unmap(AddressSpace *as, void = *buffer, hwaddr len, > cpu_notify_map_clients(); > } > =20 > +MemoryRegion *address_space_root_memory_region(AddressSpace *as) > +{ > + return as->root; > +} > + > void *cpu_physical_memory_map(hwaddr addr, > hwaddr *plen, > int is_write) This looks trivial and could've been a separate preparatory patch. Paolo, is this part okay with you? > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 7072930..9f16128 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -1076,13 +1076,6 @@ void pc_cpus_init(const char *cpu_model, DeviceS= tate *icc_bridge) > object_unref(OBJECT(cpu)); > } > =20 > - /* map APIC MMIO area if CPU has APIC */ > - if (cpu && cpu->apic_state) { > - /* XXX: what if the base changes? */ > - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, > - APIC_DEFAULT_ADDRESS, 0x1000); > - } > - > /* tell smbios about cpuid version and features */ > smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_= EDX]); > } > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c > index 0032b97..cf105f5 100644 > --- a/hw/intc/apic_common.c > +++ b/hw/intc/apic_common.c > @@ -296,7 +296,8 @@ static void apic_common_realize(DeviceState *dev, E= rror **errp) > APICCommonClass *info; > static DeviceState *vapic; > static int apic_no; > - static bool mmio_registered; > + CPUState *cpu =3D CPU(s->cpu); > + MemoryRegion *root; Nit: These variables were sorted by non-static vs. static, so the new ones should've gone before vapic. > =20 > if (apic_no >=3D MAX_APICS) { > error_setg(errp, "%s initialization failed.", > @@ -307,11 +308,12 @@ static void apic_common_realize(DeviceState *dev,= Error **errp) > =20 > info =3D APIC_COMMON_GET_CLASS(s); > info->realize(dev, errp); > - if (!mmio_registered) { > - ICCBus *b =3D ICC_BUS(qdev_get_parent_bus(dev)); > - memory_region_add_subregion(b->apic_address_space, 0, &s->io_m= emory); > - mmio_registered =3D true; > - } > + > + root =3D address_space_root_memory_region(cpu->as); > + memory_region_add_subregion_overlap(root, > + s->apicbase & MSR_IA32_APICBAS= E_BASE, > + &s->io_memory, > + 0x1000); > =20 > /* Note: We need at least 1M to map the VAPIC option ROM */ > if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && > diff --git a/include/exec/memory.h b/include/exec/memory.h > index 8ae004e..811f027 100644 > --- a/include/exec/memory.h > +++ b/include/exec/memory.h > @@ -1308,6 +1308,11 @@ void *address_space_map(AddressSpace *as, hwaddr= addr, > void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, > int is_write, hwaddr access_len); > =20 > +/* address_space_root_memory_region: get root memory region > + * > + * @as: #AddressSpace to be accessed > + */ > +MemoryRegion *address_space_root_memory_region(AddressSpace *as); > =20 > #endif > =20 > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 36b07f9..1fb88f6 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -2741,6 +2741,8 @@ static void x86_cpu_apic_create(X86CPU *cpu, Erro= r **errp) > /* TODO: convert to link<> */ > apic =3D APIC_COMMON(cpu->apic_state); > apic->cpu =3D cpu; > + cpu_set_apic_base(cpu->apic_state, > + APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE)= ; > } > =20 > static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) Otherwise, if it works now, LGTM. Regards, Andreas --=20 SUSE Linux GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Felix Imend=F6rffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG N=FCrnberg)