From mboxrd@z Thu Jan 1 00:00:00 1970 From: sboyd@codeaurora.org (Stephen Boyd) Date: Thu, 25 Jun 2015 14:35:51 -0700 Subject: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling In-Reply-To: <558C72EB.8010502@oracle.com> References: <1435242710-31346-1-git-send-email-vitalya@ti.com> <558C188B.5060107@oracle.com> <558C6C4F.1090102@codeaurora.org> <558C72EB.8010502@oracle.com> Message-ID: <558C7437.2090306@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/25/2015 02:30 PM, santosh shilimkar wrote: > On 6/25/2015 2:02 PM, Stephen Boyd wrote: >> On 06/25/2015 08:04 AM, santosh shilimkar wrote: >>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote: >>>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error >>>> handling >>>> for Keystone devices >>>> >>>> Change Log >>>> >>>> v2: >>>> - removing unused and sorting headers of keystone.c are moved to a >>>> separate >>>> patch. >>>> - l1l2 ecc and ddr3 ecc error handling are split it to separate >>>> patches >>>> - removed unused headers from keystone_ecc.c >>>> - platsmp.c removed from the patch. >>>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler >>>> - checked and handled existing echttps://lwn.net/Articles/593336/c >>>> error before enabling ddr3 interrupt >>>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware >>>> and >>>> there is no reason to handle it by software >>>> >>> This version looks good to me. As already commented, I would have liked >>> the patch 2/3(L2 ECC) code in ARM generic code so will give some more >>> time for others to come back. Otherwise I will queue this up for next >>> window. >> >> Why not make this into an edac driver? I sent out an L1/L2 error >> detection edac driver for Krait processors a year ago, but it stalled >> due to some DT binding stuff[1]. This looks fairly similar. >> > Indeed the error detection part is very similar(expected as well > considering the same processor L2 regs). I am not sure we need > full driver only for that but at least the IRQ error handler > related code can reside together. Lets see what RMK thinks > on this. > There's an existing one for highbank (drivers/edac/highbank_l2_edac.c) and there was a patch set for the pl310 as well[1]. I don't think we want any architecture specific code for this, just use the EDAC framework. [1] https://lkml.org/lkml/2014/3/2/87 -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling Date: Thu, 25 Jun 2015 14:35:51 -0700 Message-ID: <558C7437.2090306@codeaurora.org> References: <1435242710-31346-1-git-send-email-vitalya@ti.com> <558C188B.5060107@oracle.com> <558C6C4F.1090102@codeaurora.org> <558C72EB.8010502@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <558C72EB.8010502-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: santosh shilimkar , Vitaly Andrianov , ssantosh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 06/25/2015 02:30 PM, santosh shilimkar wrote: > On 6/25/2015 2:02 PM, Stephen Boyd wrote: >> On 06/25/2015 08:04 AM, santosh shilimkar wrote: >>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote: >>>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error >>>> handling >>>> for Keystone devices >>>> >>>> Change Log >>>> >>>> v2: >>>> - removing unused and sorting headers of keystone.c are moved to a >>>> separate >>>> patch. >>>> - l1l2 ecc and ddr3 ecc error handling are split it to separate >>>> patches >>>> - removed unused headers from keystone_ecc.c >>>> - platsmp.c removed from the patch. >>>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler >>>> - checked and handled existing echttps://lwn.net/Articles/593336/c >>>> error before enabling ddr3 interrupt >>>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware >>>> and >>>> there is no reason to handle it by software >>>> >>> This version looks good to me. As already commented, I would have liked >>> the patch 2/3(L2 ECC) code in ARM generic code so will give some more >>> time for others to come back. Otherwise I will queue this up for next >>> window. >> >> Why not make this into an edac driver? I sent out an L1/L2 error >> detection edac driver for Krait processors a year ago, but it stalled >> due to some DT binding stuff[1]. This looks fairly similar. >> > Indeed the error detection part is very similar(expected as well > considering the same processor L2 regs). I am not sure we need > full driver only for that but at least the IRQ error handler > related code can reside together. Lets see what RMK thinks > on this. > There's an existing one for highbank (drivers/edac/highbank_l2_edac.c) and there was a patch set for the pl310 as well[1]. I don't think we want any architecture specific code for this, just use the EDAC framework. [1] https://lkml.org/lkml/2014/3/2/87 -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752546AbbFYVgA (ORCPT ); Thu, 25 Jun 2015 17:36:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36386 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752484AbbFYVfy (ORCPT ); Thu, 25 Jun 2015 17:35:54 -0400 Message-ID: <558C7437.2090306@codeaurora.org> Date: Thu, 25 Jun 2015 14:35:51 -0700 From: Stephen Boyd User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: santosh shilimkar , Vitaly Andrianov , ssantosh@kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling References: <1435242710-31346-1-git-send-email-vitalya@ti.com> <558C188B.5060107@oracle.com> <558C6C4F.1090102@codeaurora.org> <558C72EB.8010502@oracle.com> In-Reply-To: <558C72EB.8010502@oracle.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/25/2015 02:30 PM, santosh shilimkar wrote: > On 6/25/2015 2:02 PM, Stephen Boyd wrote: >> On 06/25/2015 08:04 AM, santosh shilimkar wrote: >>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote: >>>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error >>>> handling >>>> for Keystone devices >>>> >>>> Change Log >>>> >>>> v2: >>>> - removing unused and sorting headers of keystone.c are moved to a >>>> separate >>>> patch. >>>> - l1l2 ecc and ddr3 ecc error handling are split it to separate >>>> patches >>>> - removed unused headers from keystone_ecc.c >>>> - platsmp.c removed from the patch. >>>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler >>>> - checked and handled existing echttps://lwn.net/Articles/593336/c >>>> error before enabling ddr3 interrupt >>>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware >>>> and >>>> there is no reason to handle it by software >>>> >>> This version looks good to me. As already commented, I would have liked >>> the patch 2/3(L2 ECC) code in ARM generic code so will give some more >>> time for others to come back. Otherwise I will queue this up for next >>> window. >> >> Why not make this into an edac driver? I sent out an L1/L2 error >> detection edac driver for Krait processors a year ago, but it stalled >> due to some DT binding stuff[1]. This looks fairly similar. >> > Indeed the error detection part is very similar(expected as well > considering the same processor L2 regs). I am not sure we need > full driver only for that but at least the IRQ error handler > related code can reside together. Lets see what RMK thinks > on this. > There's an existing one for highbank (drivers/edac/highbank_l2_edac.c) and there was a patch set for the pl310 as well[1]. I don't think we want any architecture specific code for this, just use the EDAC framework. [1] https://lkml.org/lkml/2014/3/2/87 -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project