From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by yocto-www.yoctoproject.org (Postfix, from userid 118) id D3C5BE00A70; Sun, 5 Jul 2015 19:45:58 -0700 (PDT) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on yocto-www.yoctoproject.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 X-Spam-HAM-Report: * -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no * trust * [69.172.196.247 listed in list.dnswl.org] * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] X-Greylist: delayed 315 seconds by postgrey-1.32 at yocto-www; Sun, 05 Jul 2015 19:45:55 PDT Received: from mx0-55.i-mecca.net (mx0-55.i-mecca.net [69.172.196.247]) by yocto-www.yoctoproject.org (Postfix) with ESMTP id 0680FE00A25 for ; Sun, 5 Jul 2015 19:45:55 -0700 (PDT) Received: from mail01.ehosting.ca (localhost [127.0.0.1]) by mx0.i-mecca.net (Postfix) with ESMTP id 84686C50DF; Sun, 5 Jul 2015 19:40:39 -0700 (PDT) Received: from mx0-ns6.i-mecca.net (unknown [192.168.1.6]) by mx0.i-mecca.net (Postfix) with ESMTP id B1F33C1C2C; Sun, 5 Jul 2015 19:40:38 -0700 (PDT) Received: from ns6.i-mecca.net (ns6 [127.0.0.1]) by ns6.i-mecca.net (Postfix) with ESMTP id A341E32E002; Sun, 5 Jul 2015 22:40:38 -0400 (EDT) Received: from kilgour.homelinux.com (S01060023beda7832.no.shawcable.net [70.67.197.25]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by ns6.i-mecca.net (Postfix) with ESMTPSA id 7D0A5282001; Sun, 5 Jul 2015 22:40:35 -0400 (EDT) Message-ID: <5599EA9E.7090503@whiterocker.com> Date: Sun, 05 Jul 2015 19:40:30 -0700 From: Chris Kilgour User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: meta-freescale@yoctoproject.org Subject: [PATCH] u-boot: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jul 2015 02:45:58 -0000 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot, but the problem was mysteriously related to the toolchain used for building u-boot. Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value. This causes the timer compare to fire 344 seconds after u-boot configures it. Depending on how fast u-boot gets the kernel booted, this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. At any rate this patch makes the manipulation explicitly 64-bit which alleviates the issue. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html Index: u-boot-2015.04/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h =================================================================== --- u-boot-2015.04.orig/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ u-boot-2015.04/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -28,7 +28,7 @@ #define RCWSR4_SRDS1_PRTCL_SHIFT 24 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 -#define TIMER_COMP_VAL 0xffffffff +#define TIMER_COMP_VAL 0xffffffffffffffffull #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) Index: u-boot-2015.04/arch/arm/cpu/armv7/ls102xa/timer.c =================================================================== --- u-boot-2015.04.orig/arch/arm/cpu/armv7/ls102xa/timer.c +++ u-boot-2015.04/arch/arm/cpu/armv7/ls102xa/timer.c @@ -58,7 +58,8 @@ int timer_init(void) struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; if (!readl( &sctr->cntcr )) { - unsigned long ctrl, val, freq; + unsigned long ctrl, freq; + unsigned long long val64; /* Enable System Counter */ writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); @@ -71,8 +72,8 @@ int timer_init(void) asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); /* Set PL1 Physical Comp Value */ - val = TIMER_COMP_VAL; - asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val)); + val64 = TIMER_COMP_VAL; + asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val64)); gd->arch.tbl = 0; gd->arch.tbu = 0;