From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH] pinctrl: bcm2835: Clear the event latch register when disabling interrupts Date: Fri, 10 Jul 2015 22:15:40 -0600 Message-ID: <55A0986C.1030905@wwwdotorg.org> References: <55927F0B.80602@raspberrypi.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55927F0B.80602-FnsA7b+Nu9XbIbC87yuRow@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-rpi-kernel" Errors-To: linux-rpi-kernel-bounces+glkr-linux-rpi-kernel=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Jonathan Bell , Linus Walleij , Lee Jones Cc: linux-gpio , linux-rpi-kernel List-Id: linux-gpio@vger.kernel.org On 06/30/2015 05:35 AM, Jonathan Bell wrote: > It's possible to hit a race condition if interrupts are generated on a GPIO > pin when the IRQ line in question is being disabled. > > If the interrupt is freed, bcm2835_gpio_irq_disable() is called which > disables the event generation sources (edge, level). If an event occurred > between the last disabling of hard IRQs and the write to the event > source registers, a bit would be set in the GPIO event detect register > (GPEDSn) which goes unacknowledged by bcm2835_gpio_irq_handler() > so Linux complains loudly. > > There is no per-GPIO mask register, so when disabling GPIO interrupts > write 1 to the relevant bit in GPEDSn to clear out any stale events. Acked-by: Stephen Warren (Sorry for the slow response; I was on vacation)