Re: [Qemu-devel] [PATCH] target-mips: apply workaround for TCG optimizations for MFC1

[Paolo Bonzini <pbonzini@redhat.com>]

On 15/07/2015 12:14, Aurelien Jarno wrote:
> I think for 2.4 we should go with the ADDR32 way, using the following
> kind of patch. It works when %gs is in use, but has to be extended when
> it's not in use. The idea is that qemu_ld/st should behave like other
> 32-bit ops, that is ignore the high part of the register.
> 
> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
> index ff4d9cf..e139c44 100644
> --- a/tcg/i386/tcg-target.c
> +++ b/tcg/i386/tcg-target.c
> @@ -1572,6 +1572,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
>          if (GUEST_BASE && guest_base_flags) {
>              seg = guest_base_flags;
>              offset = 0;
> +            if (TARGET_LONG_BITS == 32) {
> +                seg = P_ADDR32;
> +            }
>          } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
>              tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE);
>              tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base);
> @@ -1705,6 +1708,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
>          if (GUEST_BASE && guest_base_flags) {
>              seg = guest_base_flags;
>              offset = 0;
> +            if (TARGET_LONG_BITS == 32) {
> +                seg = P_ADDR32;
> +            }
>          } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
>              tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE);
>              tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base);
> 
> 

Yup, I'll post the aarch64 changes too.

Paolo