From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOG8-0005Q3-MZ for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:06:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFOG4-0000Aj-Lc for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:06:08 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:50111) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOG4-0000AY-Fq for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:06:04 -0400 Message-ID: <55A676D8.7090502@imgtec.com> Date: Wed, 15 Jul 2015 16:06:00 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1436968536-24106-1-git-send-email-aurelien@aurel32.net> In-Reply-To: <1436968536-24106-1-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH for-2.4] tcg/i386: ignore high bits for user mode 32-bit qemu_ld/st List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson On 15/07/2015 14:55, Aurelien Jarno wrote: > For a 64-bit host not implementing the trunc_shr_i32 op, the high bits > of a register should be ignored for 32-bit ops. This is currently not > the case of qemu_ld/st ops in user mode. > > Fix that by either using the ADDR32 prefix (in case GUEST_BASE == 0 or > a segment register is in use), or by doing an explicit zero-extension. > The zero-extension can be done in place as we know the registers holds > a 32-bit value. > > Reported-by: Leon Alrae > Cc: Leon Alrae > Cc: Paolo Bonzini > Cc: Richard Henderson > Signed-off-by: Aurelien Jarno > --- > tcg/i386/tcg-target.c | 44 ++++++++++++++++++++++++++++++++------------ > 1 file changed, 32 insertions(+), 12 deletions(-) Tested-by: Leon Alrae Thanks for looking into this! Leon