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From: Leon Alrae <leon.alrae@imgtec.com>
To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Subject: Re: [Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for LWL/LWR/LDL/LDR
Date: Wed, 15 Jul 2015 17:30:10 +0100	[thread overview]
Message-ID: <55A68A92.5000401@imgtec.com> (raw)
In-Reply-To: <1436888717-8122-2-git-send-email-aurelien@aurel32.net>

On 14/07/2015 16:45, Aurelien Jarno wrote:
> When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU
> currently reports the aligned address in CP0 BadVAddr, while the Windows
> NT kernel expects the unaligned address.
> 
> This patch adds a byte access with the unaligned address at the
> beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page
> fault and fill the QEMU TLB.
> 
> Cc: Leon Alrae <leon.alrae@imgtec.com>
> Reported-by: Hervé Poussineau <hpoussin@reactos.org>
> Tested-by: Hervé Poussineau <hpoussin@reactos.org>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-mips/translate.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Thanks, applied to mips-next.

Leon

  reply	other threads:[~2015-07-15 16:30 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-14 15:45 [Qemu-devel] [PATCH 0/2] target-mips: fix Windows NT support Aurelien Jarno
2015-07-14 15:45 ` [Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for LWL/LWR/LDL/LDR Aurelien Jarno
2015-07-15 16:30   ` Leon Alrae [this message]
2015-07-14 15:45 ` [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation Aurelien Jarno
2015-07-14 16:17   ` Paolo Bonzini
2015-07-14 16:45     ` Aurelien Jarno
2015-07-14 17:11       ` Paolo Bonzini

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