From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sekhar Nori Subject: Re: [PATCH v2] gpio/davinci: add interrupt support for GPIOs 16-31 Date: Thu, 16 Jul 2015 14:34:54 +0530 Message-ID: <55A773B6.7030906@ti.com> References: <1435861890-23147-1-git-send-email-vitalya@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1435861890-23147-1-git-send-email-vitalya@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: Vitaly Andrianov , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, gnurou@gmail.com, linus.walleij@linaro.org, grygorii.strashko@ti.com, m-karicheri2@ti.com List-Id: linux-gpio@vger.kernel.org On Friday 03 July 2015 12:01 AM, Vitaly Andrianov wrote: > Interrupts for GPIOs 16 through 31 are enabled by bit 1 in the > "binten" register (offset 8). Previous versions of GPIO only > used bit 0, which enables GPIO 0-15 interrupts. > > Signed-off-by: Vitaly Andrianov > Reviewed-by: Grygorii Strashko Reviewed-by: Sekhar Nori Thanks, Sekhar From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932077AbbGPJFB (ORCPT ); Thu, 16 Jul 2015 05:05:01 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:37467 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752224AbbGPJE7 (ORCPT ); Thu, 16 Jul 2015 05:04:59 -0400 Message-ID: <55A773B6.7030906@ti.com> Date: Thu, 16 Jul 2015 14:34:54 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Vitaly Andrianov , , , , , , Subject: Re: [PATCH v2] gpio/davinci: add interrupt support for GPIOs 16-31 References: <1435861890-23147-1-git-send-email-vitalya@ti.com> In-Reply-To: <1435861890-23147-1-git-send-email-vitalya@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 03 July 2015 12:01 AM, Vitaly Andrianov wrote: > Interrupts for GPIOs 16 through 31 are enabled by bit 1 in the > "binten" register (offset 8). Previous versions of GPIO only > used bit 0, which enables GPIO 0-15 interrupts. > > Signed-off-by: Vitaly Andrianov > Reviewed-by: Grygorii Strashko Reviewed-by: Sekhar Nori Thanks, Sekhar