From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGMRe-0000fT-W9 for qemu-devel@nongnu.org; Sat, 18 Jul 2015 03:22:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZGMRb-0004EY-QK for qemu-devel@nongnu.org; Sat, 18 Jul 2015 03:22:02 -0400 Received: from mail-wi0-x22b.google.com ([2a00:1450:400c:c05::22b]:34395) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGMRb-0004Dp-Iy for qemu-devel@nongnu.org; Sat, 18 Jul 2015 03:21:59 -0400 Received: by wibud3 with SMTP id ud3so53200554wib.1 for ; Sat, 18 Jul 2015 00:21:57 -0700 (PDT) Sender: Richard Henderson References: <20150715205423.GA23115@aurel32.net> <55A82251.6020308@twiddle.net> <20150717102350.GA15281@aurel32.net> <20150717134247.GA4343@aurel32.net> From: Richard Henderson Message-ID: <55A9FE91.7040103@twiddle.net> Date: Sat, 18 Jul 2015 08:21:53 +0100 MIME-Version: 1.0 In-Reply-To: <20150717134247.GA4343@aurel32.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 00/13] tcg/sparc v8plus code generation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: Paolo Bonzini , qemu-devel@nongnu.org On 07/17/2015 02:42 PM, Aurelien Jarno wrote: > On 2015-07-17 12:23, Aurelien Jarno wrote: >> On 2015-07-16 22:29, Richard Henderson wrote: >>> On 07/15/2015 09:54 PM, Aurelien Jarno wrote: >>>> While I understand why we need the new trunc_shr_i32 opcode for MIPS64 >>>> (the 32-bit values must be kept sign-extended), I currently fail to >>>> see why it is needed for SPARC. >>> >>> As far as I recall, it improves code for extracting high parts of 64-bit >>> quantities. Without this, we wind up with a 64-bit shift, requiring a >>> 64-bit temp register, followed by the "real" truncate which can copy the >>> data to a 32-bit destination register. >> >> Ok, I understand the use case now. So it's not for correctness, but >> rather to generate more optimized code. > > OTOH, it means that we always have to go through a 32-bit register first > when truncating a 64-bit value. > > I mean we gain in the following case: > shr_i64 t64, t64, i > trunc_i64_i32 t32, t64 > ... > > But we lose in the following case: > trunc_i64_i32 t32, t64 > neg t32, t32 > ... Why do you beleive we're using an extra temp here? Certainly you can't "neg t32, t64" in any circumstance. Anyway, this comes up most often with interfacing with the sparcv8plus calling convention, in which 64-bit quantities must be passed in 2 registers. Before, we'd emit code like shrx %g2, 32, %g1 mov %g1, %o0 mov %g2, %o1 After, we're able to put the shift output directly to %o0. r~