From: "Siluvery, Arun" <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Change SRM, LRM instructions to use correct length
Date: Mon, 20 Jul 2015 13:55:01 +0100 [thread overview]
Message-ID: <55ACEFA5.50206@linux.intel.com> (raw)
In-Reply-To: <1437059974-26575-1-git-send-email-arun.siluvery@linux.intel.com>
On 16/07/2015 16:19, Arun Siluvery wrote:
> MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
> variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
> (reg, addr) pairs so use fixed length for these instructions.
>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
ping? to any reviewers?
regards
Arun
> drivers/gpu/drm/i915/i915_cmd_parser.c | 8 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 430571b..3771922 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -124,14 +124,14 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
> CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
> CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
> .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
> - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
> + CMD( MI_STORE_REGISTER_MEM, SMI, F, 1, W | B,
> .reg = { .offset = 1, .mask = 0x007FFFFC },
> .bits = {{
> .offset = 0,
> .mask = MI_GLOBAL_GTT,
> .expected = 0,
> }}, ),
> - CMD( MI_LOAD_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
> + CMD( MI_LOAD_REGISTER_MEM, SMI, F, 1, W | B,
> .reg = { .offset = 1, .mask = 0x007FFFFC },
> .bits = {{
> .offset = 0,
> @@ -1021,7 +1021,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
> * only MI_LOAD_REGISTER_IMM commands.
> */
> if (reg_addr == OACONTROL) {
> - if (desc->cmd.value == MI_LOAD_REGISTER_MEM(1)) {
> + if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
> DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
> return false;
> }
> @@ -1035,7 +1035,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
> * allowed mask/value pair given in the whitelist entry.
> */
> if (reg->mask) {
> - if (desc->cmd.value == MI_LOAD_REGISTER_MEM(1)) {
> + if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
> DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
> reg_addr);
> return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bd13494..cc3cb3e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -342,8 +342,8 @@
> */
> #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
> #define MI_LRI_FORCE_POSTED (1<<12)
> -#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
> -#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
> +#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
> +#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
> #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> @@ -354,8 +354,8 @@
> #define MI_INVALIDATE_BSD (1<<7)
> #define MI_FLUSH_DW_USE_GTT (1<<2)
> #define MI_FLUSH_DW_USE_PPGTT (0<<2)
> -#define MI_LOAD_REGISTER_MEM(x) MI_INSTR(0x29, 2*(x)-1)
> -#define MI_LOAD_REGISTER_MEM_GEN8(x) MI_INSTR(0x29, 3*(x)-1)
> +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
> +#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
> #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
> #define MI_BATCH_NON_SECURE (1)
> /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 472c544..a78c823 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11053,10 +11053,10 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> DERRMR_PIPEB_PRI_FLIP_DONE |
> DERRMR_PIPEC_PRI_FLIP_DONE));
> if (IS_GEN8(dev))
> - intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
> + intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
> MI_SRM_LRM_GLOBAL_GTT);
> else
> - intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
> + intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
> MI_SRM_LRM_GLOBAL_GTT);
> intel_ring_emit(ring, DERRMR);
> intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 7668e9b..19495ba 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1097,7 +1097,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
> {
> uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
>
> - wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) |
> + wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
> MI_SRM_LRM_GLOBAL_GTT));
> wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
> wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
> @@ -1115,7 +1115,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
> wa_ctx_emit(batch, index, 0);
> wa_ctx_emit(batch, index, 0);
>
> - wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8(1) |
> + wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
> MI_SRM_LRM_GLOBAL_GTT));
> wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
> wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
>
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next prev parent reply other threads:[~2015-07-20 12:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-16 15:19 [PATCH] drm/i915: Change SRM, LRM instructions to use correct length Arun Siluvery
2015-07-20 12:55 ` Siluvery, Arun [this message]
2015-08-04 14:43 ` Mika Kuoppala
2015-08-04 15:22 ` [PATCH v2] " Arun Siluvery
2015-08-11 14:38 ` shuang.he
2015-08-19 13:46 ` Mika Kuoppala
2015-08-26 6:45 ` Daniel Vetter
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