Re: [PATCH v3 07/32] xen/x86: fix arch_set_info_guest for HVM guests

["Roger Pau Monné" <roger.pau@citrix.com>]

El 24/07/15 a les 14.44, Jan Beulich ha escrit:
>>>> On 24.07.15 at 14:11, <roger.pau@citrix.com> wrote:
>> It seems kind of pointless IMHO, the reason to have the union is to be
>> able to access the registers using the native nomenclature, but if a
>> register doesn't exist in a specific bitness I don't see the point of
>> adding such "invalid" names.
> 
> No - put side by side an item valid in only a subset modes and an
> item only valid outside of that subset.

OK, let me see if I got that right.

>> Or your idea was to put all the bitness specific registers inside of
>> another separate structure and then unionize them? AFAICT the 16 and
>> 32bit structures are going to be empty.
> 
> How that? 64-bit mode e.g. doesn't need full descriptor data for
> many of the segment registers.

Please bear with me, but AFAIK cs, ds, es and ss still need to point to 
a GDT entry with a 0 base and a limit of 2^64.

What about the following layout:

#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
/* Anonymous union includes 16-, 32- and 64-bit names (e.g., bp/ebp/rbp). */
# define __DECL_REG(n64, n32, n16) union {     \
        uint64_t n64;                          \
        uint32_t n32;                          \
        uint16_t n16;                          \
    }
#else
/* Non-gcc sources must always use the proper 64-bit name (e.g., rbp). */
#define __DECL_REG(n64, n32, n16) uint64_t n64
#endif

#define __DECL_GP_REG(n) __DECL_REG(r##n, e##n, n)

struct cpu_x86_16 {
    /* Control registers. */
    uint32_t cr[8];
    /* Debug registers. */
    uint32_t dr[8];
    /* GDT descriptor address. */
    uint16_t gdtr;
};

struct cpu_x86_32 {
    /* Control registers. */
    uint32_t cr[8];
    /* Debug registers. */
    uint32_t dr[8];
    /* GDT descriptor address. */
    uint32_t gdtr;
};

struct cpu_x86_64 {
    /* Additional amd64 general purpose registers. */
    uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
    /* Control registers. */
    uint64_t cr[9];
    /* Debug registers. */
    uint64_t dr[8];
    /* Extended Feature Enable Register. */
    uint64_t efer;
    /* GDT descriptor address. */
    uint64_t gdtr;
};

struct cpu_hvm_regs {
    /* General purpose registers. */
    __DECL_GP_REG(ax);
    __DECL_GP_REG(bx);
    __DECL_GP_REG(cx);
    __DECL_GP_REG(dx);

    /* Index registers. */
    __DECL_GP_REG(di);
    __DECL_GP_REG(si);

    /* Pointer registers. */
    __DECL_GP_REG(bp);
    __DECL_GP_REG(sp);

    /* Instruction pointer. */
    __DECL_GP_REG(ip);

    /* Status register. */
    __DECL_GP_REG(flags);

    /* Segment registers. */
    uint16_t cs;
    uint16_t ds;
    uint16_t es;
    uint16_t ss;
    uint16_t fs;
    uint16_t gs;

    /* Task state segment. */
    uint16_t ts;

    /* Bitness specific registers. */
    union {
        struct cpu_x86_16 x86_16;
        struct cpu_x86_32 x86_32;
        struct cpu_x86_64 x86_64;
    };
};

struct vcpu_hvm_context {
/* 16bit fields of the strucutre will be used. */
#define _VCPUHVM_MODE_16B              0
#define VCPUHVM_MODE_16B               (1<<_VCPUHVM_MODE_16B)
/* 32bit fields of the structure will be used. */
#define _VCPUHVM_MODE_32B              1
#define VCPUHVM_MODE_32B               (1<<_VCPUHVM_MODE_32B)
/* 64bit fields of the structure will be used. */
#define _VCPUHVM_MODE_64B              2
#define VCPUHVM_MODE_64B               (1<<_VCPUHVM_MODE_64B)
    uint32_t flags;                         /* VCPUHVM_* flags.   */
    struct cpu_hvm_regs user_regs;          /* CPU registers.     */
};

#undef __DECL_GP_REG
#undef __DECL_REG