Re: [PATCH 00/18] Redesign of dmc firmware loading.

[Sunil Kamath <sunil.kamath@intel.com>]

On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote:
> Display microcontroller(DMC) used to save and restore display engine status
> while entering into low power display states for gen9 platform.
> Though skylake and broxton both are gen9 platform but dmc act diferently.
> Skylake is solely dependednt on dmc for entering into low power
> state - namely dc5 and dc6. Whereas broxton has low power state
> dc5 and dc9 and dc9 does not need dmc.
>
> As both gen9 platforms behaviour is different with respect to dmc,
> so software design will be different and follow the below design
> principles.

Thanks Animesh for pushing these latest patches in sequence. [including 
all latest bug fix and firmware load design change request].
With this we can already discard my older BXT specific DMC patches.

Also below SKL patches are very important to be merged asap. As they fix 
some of the major issues to achieve PC10.[which was blocked because of 
DMC DC6].

Will start reviewing right away.


Though we have positive test results already, need a detailed review to 
ensure that both SKL/BXT everything taken care also compatible with all 
linux distros.

-Sunil

>
> For skylake:
> ------------
> If firmware loading is successful,
> - Driver can goto D3 in suspend time.
> - Will not disable power-well-1 as dmc will handle save/restore/shutdown.
> If firmware loading is failed,
> - Leak rpm which will block D3 in suspend.
> - Will disable power-well-1 which will save some power.
>
> For broxton:
> ------------
> Irrespective of firmware loading succesful/failed driver should not
> block D3 during suspend as dc9 (lowest possible state) is independent
> of dmc and will not block disable call of power-well-1.
>
> During debugging PC10 entry issue for skylake found below observation,
> - dmc will get confuse if driver already disable power-well-1 during
> dc6 entry and will not work as expected.
> - The above same applicable for cdclk pll as well.
> - mmio read/write after dc6 trigger will cause display engine hang.
>
> Based on Daniel's review comments and thiinking of above pointers
> following patches is created.
>
> Animesh Manna (10):
>    drm/i915/bxt: Path added of dmc firmware ver1 for BXT
>    drm/i915/bxt: Modified HAS_CSR, added support for BXT.
>    drm/i915/bxt: Stepping info added for bxt.
>    drm/i915/gen9: block disable call for pw1 if dmc firmware is present.
>    drm/i915/gen9: csr_init after runtime pm enable
>    drm/i915/gen9: Use flush_work to synchronize with dmc loader
>    drm/i915/skl: Making DC6 entry is the last call in suspend flow.
>    drm/i915/skl: Do not disable cdclk PLL if csr firmware is present.
>    drm/i915/skl: Removed csr firmware load in resume path.
>    drm/i915/gen9: Removed byte swapping for csr firmware.
>
> Daniel Vetter (8):
>    drm/i915/gen9: move assert_csr_loaded into intel_rpm.c
>    drm/i915/gen9: Remove csr.state, csr_lock and related code.
>    drm/i915/gen9: Align line continuations in intel_csr.c.
>    drm/i915/gen9: Simplify csr loading failure printing.
>    drm/i915/gen9: extract parse_csr_fw.
>    drm/i915/gen9: Don't try to load garbage dmc firmware on resume
>    drm/i915/gen9: Use dev_priv in csr functions
>    drm/i915: Use request_firmware and our own async work
>
>   drivers/gpu/drm/i915/i915_dma.c         |  11 +-
>   drivers/gpu/drm/i915/i915_drv.c         |  33 +----
>   drivers/gpu/drm/i915/i915_drv.h         |  16 +--
>   drivers/gpu/drm/i915/i915_reg.h         |  16 +++
>   drivers/gpu/drm/i915/intel_csr.c        | 245 ++++++++++++--------------------
>   drivers/gpu/drm/i915/intel_display.c    |  11 +-
>   drivers/gpu/drm/i915/intel_drv.h        |  12 +-
>   drivers/gpu/drm/i915/intel_runtime_pm.c |  47 +++---
>   8 files changed, 155 insertions(+), 236 deletions(-)
>

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