From mboxrd@z Thu Jan 1 00:00:00 1970 From: Roger Quadros Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Date: Mon, 27 Jul 2015 12:34:00 +0300 Message-ID: <55B5FB08.7060503@ti.com> References: <1437140844-6032-1-git-send-email-rogerq@ti.com> <1437140844-6032-3-git-send-email-rogerq@ti.com> <55ACE4B5.7000107@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55ACE4B5.7000107@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: Tero Kristo , kishon@ti.com, tony@atomide.com Cc: nm@ti.com, nsekhar@ti.com, balbi@ti.com, grygorii.strashko@ti.com, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-omap@vger.kernel.org On 20/07/15 15:08, Tero Kristo wrote: > On 07/17/2015 04:47 PM, Roger Quadros wrote: >> This register is required to be passed to the SATA PHY driver >> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). >> >> Signed-off-by: Roger Quadros >> --- >> arch/arm/boot/dts/dra7.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >> index 8f1e25b..4a0718c 100644 >> --- a/arch/arm/boot/dts/dra7.dtsi >> +++ b/arch/arm/boot/dts/dra7.dtsi >> @@ -1140,6 +1140,7 @@ >> ctrl-module = <&omap_control_sata>; >> clocks = <&sys_clkin1>, <&sata_ref_clk>; >> clock-names = "sysclk", "refclk"; >> + syscon-pllreset = <&scm_conf 0x3fc>; >> #phy-cells = <0>; >> }; >> >> > > Looks fine to me. > > Make sure you use this register via regmap_update_bits only, seeing there is another potential user for the same register. Yes. Patch 1 is the user using regmap_update_bits. cheers, -roger From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754778AbbG0JeK (ORCPT ); Mon, 27 Jul 2015 05:34:10 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:42882 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754201AbbG0JeG (ORCPT ); Mon, 27 Jul 2015 05:34:06 -0400 Message-ID: <55B5FB08.7060503@ti.com> Date: Mon, 27 Jul 2015 12:34:00 +0300 From: Roger Quadros User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Tero Kristo , , CC: , , , , , Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY References: <1437140844-6032-1-git-send-email-rogerq@ti.com> <1437140844-6032-3-git-send-email-rogerq@ti.com> <55ACE4B5.7000107@ti.com> In-Reply-To: <55ACE4B5.7000107@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/07/15 15:08, Tero Kristo wrote: > On 07/17/2015 04:47 PM, Roger Quadros wrote: >> This register is required to be passed to the SATA PHY driver >> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). >> >> Signed-off-by: Roger Quadros >> --- >> arch/arm/boot/dts/dra7.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >> index 8f1e25b..4a0718c 100644 >> --- a/arch/arm/boot/dts/dra7.dtsi >> +++ b/arch/arm/boot/dts/dra7.dtsi >> @@ -1140,6 +1140,7 @@ >> ctrl-module = <&omap_control_sata>; >> clocks = <&sys_clkin1>, <&sata_ref_clk>; >> clock-names = "sysclk", "refclk"; >> + syscon-pllreset = <&scm_conf 0x3fc>; >> #phy-cells = <0>; >> }; >> >> > > Looks fine to me. > > Make sure you use this register via regmap_update_bits only, seeing there is another potential user for the same register. Yes. Patch 1 is the user using regmap_update_bits. cheers, -roger