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From: Michel Thierry <michel.thierry@intel.com>
To: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Cc: "Goel, Akash" <akash.goel@intel.com>
Subject: Re: [PATCH v5 11/19] drm/i915/gen8: Initialize PDPs
Date: Wed, 29 Jul 2015 15:35:14 +0100	[thread overview]
Message-ID: <55B8E4A2.5060808@intel.com> (raw)
In-Reply-To: <1437039211-2507-12-git-send-email-michel.thierry@intel.com>

On 7/16/2015 10:33 AM, Michel Thierry wrote:
> Similar to PDs, while setting up a page directory pointer, make all entries
> of the pdp point to the scratch pd before mapping (and make all its entries
> point to the scratch page); this is to be safe in case of out of bound
> access or proactive prefetch.
>
> v2: Handle scratch_pdp allocation failure correctly, and keep
> initialize_px functions together (Akash)
> v3: Rebase after Mika's ppgtt cleanup / scratch merge patch series. Rely on
> the added macros to initialize the pdps.
> v4: Rebase after final merged version of Mika's ppgtt/scratch patches
> (and removed commit message part related to v3).
>
> Suggested-by: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 38 +++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
>   2 files changed, 39 insertions(+)
>

This patch also initializes the PML4 so it should say so (I'll also add 
text about the scratch pdp, which the PML4 entries point to).
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  reply	other threads:[~2015-07-29 14:35 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-16  9:33 [PATCH v5 00/19] 48-bit PPGTT Michel Thierry
2015-07-16  9:33 ` [PATCH v5 01/19] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-16  9:33 ` [PATCH v5 02/19] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-16  9:33 ` [PATCH v5 03/19] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-16  9:33 ` [PATCH v5 04/19] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-16  9:33 ` [PATCH v5 05/19] drm/i915/gen8: Add PML4 structure Michel Thierry
2015-07-16  9:33 ` [PATCH v5 06/19] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-29 14:34   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 07/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-29 14:34   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 08/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-29 14:35   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 09/19] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-16  9:33 ` [PATCH v5 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-16  9:33 ` [PATCH v5 11/19] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-07-29 14:35   ` Michel Thierry [this message]
2015-07-16  9:33 ` [PATCH v5 12/19] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-16  9:33 ` [PATCH v5 13/19] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-16  9:33 ` [PATCH v5 14/19] drm/i915: object size needs to be u64 Michel Thierry
2015-07-16  9:33 ` [PATCH v5 15/19] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-16  9:33 ` [PATCH v5 16/19] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-16  9:33 ` [PATCH v5 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-27 14:34   ` Goel, Akash
2015-07-27 14:46     ` Chris Wilson
2015-07-27 14:53       ` Michel Thierry
2015-07-27 21:11   ` Chris Wilson
2015-07-28 11:12     ` Michel Thierry
2015-07-28 14:43       ` Chris Wilson
2015-07-29 11:05         ` Michel Thierry
2015-07-29 11:17           ` Chris Wilson
2015-07-16  9:33 ` [PATCH v5 18/19] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-16  9:33 ` [PATCH v5 19/19] drm/i915: Save some page table setup on repeated binds Michel Thierry
2015-07-28 12:18 ` [PATCH v5 00/19] 48-bit PPGTT Chris Wilson

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