diff for duplicates of <55B9DB0E.7010303@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 90e0aa1..ea506e6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ On 07/22/2015 11:39 AM, Jisheng Zhang wrote: > It also adds dts file for Marvell Berlin4CT DMP board which is > based on Berlin4CT SoC. > -> Signed-off-by: Jisheng Zhang <jszhang@marvell.com> +> Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> > --- [...] > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts @@ -17,7 +17,7 @@ On 07/22/2015 11:39 AM, Jisheng Zhang wrote: > +/* > + * Copyright (C) 2015 Marvell Technology Group Ltd. > + * -> + * Author: Jisheng Zhang <jszhang@marvell.com> +> + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> [...] > +/ { @@ -55,7 +55,7 @@ Are you fine with fixing the broken CAPSLOCK key, i.e. make above > +/* > + * Copyright (C) 2015 Marvell Technology Group Ltd. > + * -> + * Author: Jisheng Zhang <jszhang@marvell.com> +> + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> [...] > + > +/ { @@ -85,7 +85,7 @@ of the soc {} node. Sebastian -> + gic: interrupt-controller at 901000 { +> + gic: interrupt-controller@901000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; @@ -96,14 +96,14 @@ Sebastian > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + apb at fc0000 { +> + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + -> + sic: interrupt-controller at 1000 { +> + sic: interrupt-controller@1000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x1000 0x30>; > + interrupt-controller; @@ -112,7 +112,7 @@ Sebastian > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + uart0: uart at d000 { +> + uart0: uart@d000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xd000 0x100>; > + interrupts = <8>; @@ -124,3 +124,7 @@ Sebastian > + }; > +}; > +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 02588cd..3c8f022 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,23 @@ "ref\01437557992-7111-1-git-send-email-jszhang@marvell.com\0" "ref\01437557992-7111-2-git-send-email-jszhang@marvell.com\0" - "From\0sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)\0" - "Subject\0[PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" + "ref\01437557992-7111-2-git-send-email-jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org\0" + "From\0Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" "Date\0Thu, 30 Jul 2015 10:06:38 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>" + catalin.marinas-5wv7dgnIgG8@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + sudeep.holla-5wv7dgnIgG8@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + " pawel.moll-5wv7dgnIgG8@public.gmane.org\0" + "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "On 07/22/2015 11:39 AM, Jisheng Zhang wrote:\n" @@ -13,7 +27,7 @@ "> It also adds dts file for Marvell Berlin4CT DMP board which is\n" "> based on Berlin4CT SoC.\n" ">\n" - "> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>\n" + "> Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "> ---\n" "[...]\n" "> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts\n" @@ -25,7 +39,7 @@ "> +/*\n" "> + * Copyright (C) 2015 Marvell Technology Group Ltd.\n" "> + *\n" - "> + * Author: Jisheng Zhang <jszhang@marvell.com>\n" + "> + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "[...]\n" "> +/ {\n" "\n" @@ -63,7 +77,7 @@ "> +/*\n" "> + * Copyright (C) 2015 Marvell Technology Group Ltd.\n" "> + *\n" - "> + * Author: Jisheng Zhang <jszhang@marvell.com>\n" + "> + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "[...]\n" "> +\n" "> +/ {\n" @@ -93,7 +107,7 @@ "\n" "Sebastian\n" "\n" - "> +\t\tgic: interrupt-controller at 901000 {\n" + "> +\t\tgic: interrupt-controller@901000 {\n" "> +\t\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t\tinterrupt-controller;\n" @@ -104,14 +118,14 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb at fc0000 {\n" + "> +\t\tapb@fc0000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 0xfc0000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&sic>;\n" "> +\n" - "> +\t\t\tsic: interrupt-controller at 1000 {\n" + "> +\t\t\tsic: interrupt-controller@1000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-ictl\";\n" "> +\t\t\t\treg = <0x1000 0x30>;\n" "> +\t\t\t\tinterrupt-controller;\n" @@ -120,7 +134,7 @@ "> +\t\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0: uart at d000 {\n" + "> +\t\t\tuart0: uart@d000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0xd000 0x100>;\n" "> +\t\t\t\tinterrupts = <8>;\n" @@ -131,6 +145,10 @@ "> +\t\t};\n" "> +\t};\n" "> +};\n" - > + ">\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -48ff67fa1998c8fde3b375f1f37d7a298a7426c691a46838adde1d7e7c111e0f +deff89674bd9383661fb10a8ec9828f38253fe764d65f64d8da44b482c2ea531
diff --git a/a/1.txt b/N2/1.txt index 90e0aa1..1452b0b 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -85,7 +85,7 @@ of the soc {} node. Sebastian -> + gic: interrupt-controller at 901000 { +> + gic: interrupt-controller@901000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; @@ -96,14 +96,14 @@ Sebastian > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + apb at fc0000 { +> + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + -> + sic: interrupt-controller at 1000 { +> + sic: interrupt-controller@1000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x1000 0x30>; > + interrupt-controller; @@ -112,7 +112,7 @@ Sebastian > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + uart0: uart at d000 { +> + uart0: uart@d000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xd000 0x100>; > + interrupts = <8>; diff --git a/a/content_digest b/N2/content_digest index 02588cd..82cb454 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,22 @@ "ref\01437557992-7111-1-git-send-email-jszhang@marvell.com\0" "ref\01437557992-7111-2-git-send-email-jszhang@marvell.com\0" - "From\0sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)\0" - "Subject\0[PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" + "From\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" + "Subject\0Re: [PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" "Date\0Thu, 30 Jul 2015 10:06:38 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jisheng Zhang <jszhang@marvell.com>" + catalin.marinas@arm.com + will.deacon@arm.com + khilman@linaro.org + arnd@arndb.de + olof@lixom.net + mark.rutland@arm.com + sudeep.holla@arm.com + robh+dt@kernel.org + galak@codeaurora.org + " pawel.moll@arm.com\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + linux-kernel@vger.kernel.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "On 07/22/2015 11:39 AM, Jisheng Zhang wrote:\n" @@ -93,7 +106,7 @@ "\n" "Sebastian\n" "\n" - "> +\t\tgic: interrupt-controller at 901000 {\n" + "> +\t\tgic: interrupt-controller@901000 {\n" "> +\t\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t\tinterrupt-controller;\n" @@ -104,14 +117,14 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb at fc0000 {\n" + "> +\t\tapb@fc0000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 0xfc0000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&sic>;\n" "> +\n" - "> +\t\t\tsic: interrupt-controller at 1000 {\n" + "> +\t\t\tsic: interrupt-controller@1000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-ictl\";\n" "> +\t\t\t\treg = <0x1000 0x30>;\n" "> +\t\t\t\tinterrupt-controller;\n" @@ -120,7 +133,7 @@ "> +\t\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0: uart at d000 {\n" + "> +\t\t\tuart0: uart@d000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0xd000 0x100>;\n" "> +\t\t\t\tinterrupts = <8>;\n" @@ -133,4 +146,4 @@ "> +};\n" > -48ff67fa1998c8fde3b375f1f37d7a298a7426c691a46838adde1d7e7c111e0f +0617c65185008eba9b9db288b6a250e442221741aa08b543999aac036cee9636
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