From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use
Date: Thu, 30 Jul 2015 12:41:23 -0600 [thread overview]
Message-ID: <55BA6FD3.8000509@wwwdotorg.org> (raw)
In-Reply-To: <1438200801-10888-1-git-send-email-twarren@nvidia.com>
On 07/29/2015 02:13 PM, Tom Warren wrote:
> Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
> to be measured - should be close to 700MHz (1.4G/2).
>
> Note that some freqs aren't in the PLLU table in T210 TRM
> (13, 26MHz), so I used the 12MHz table entry for them. They
> shouldn't be selected since they're not viable T210 OSC freqs.
>
> Since there are now 2 new OSC defines, all tables (pll_x_table,
> PLLU) had to increase by two entries, but since 38.4/48MHz are
> not viable osc freqs on T20/30/114, etc, they're just set to 0.
I didn't look at all of the numbers in detail, but these patches look
like a step in the right direction, so the series,
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
(tested upstream this time)
prev parent reply other threads:[~2015-07-30 18:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-29 20:13 [U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use Tom Warren
2015-07-29 20:13 ` [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc Tom Warren
2015-08-04 8:32 ` Marcel Ziswiler
2015-08-04 15:36 ` Tom Warren
2015-08-05 14:19 ` Marcel Ziswiler
2015-08-10 12:58 ` Simon Glass
2015-07-30 18:41 ` Stephen Warren [this message]
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