From mboxrd@z Thu Jan 1 00:00:00 1970 From: michal.simek@xilinx.com (Michal Simek) Date: Tue, 4 Aug 2015 10:18:54 +0200 Subject: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. In-Reply-To: <1438675772.3793.18.camel@pengutronix.de> References: <1438305237-18497-1-git-send-email-moritz.fischer@ettus.com> <1438305237-18497-2-git-send-email-moritz.fischer@ettus.com> <1438675772.3793.18.camel@pengutronix.de> Message-ID: <55C0756E.8050003@xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08/04/2015 10:09 AM, Philipp Zabel wrote: > Hi Moritz, > > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer: >> Signed-off-by: Moritz Fischer >> --- >> .../devicetree/bindings/reset/zynq-reset.txt | 68 ++++++++++++++++++++++ >> 1 file changed, 68 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt >> new file mode 100644 >> index 0000000..498c037a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt >> @@ -0,0 +1,68 @@ >> +Xilinx Zynq Reset Manager >> + >> +The Zynq AP-SoC has several different resets. >> + >> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. >> + >> +Required properties: >> +- compatible: "xlnx,zynq-reset" >> +- reg: SLCR offset and size taken via syscon <0x200 0x48> >> +- syscon: <&slcr> >> + This should be a phandle to the Zynq's SLCR register. > > ^ register singular? > > I still think the syscon phandle property is superfluous, > but I'm fine with keeping it for consistency. > It could always be made optional later. Great. Philipp: I expect you want to take at least 1/4 and 3/4 via your tree. I am fine if you also want to add 2/4 and 4/4 via your tree. If you think that they should go via arm-soc please let me know and I will add them to the queue. Thanks, Michal From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Subject: Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. Date: Tue, 4 Aug 2015 10:18:54 +0200 Message-ID: <55C0756E.8050003@xilinx.com> References: <1438305237-18497-1-git-send-email-moritz.fischer@ettus.com> <1438305237-18497-2-git-send-email-moritz.fischer@ettus.com> <1438675772.3793.18.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1438675772.3793.18.camel@pengutronix.de> Sender: linux-kernel-owner@vger.kernel.org To: Philipp Zabel , Moritz Fischer Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, galak@codeaurora.org, soren.brinkmann@xilinx.com List-Id: devicetree@vger.kernel.org On 08/04/2015 10:09 AM, Philipp Zabel wrote: > Hi Moritz, > > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer: >> Signed-off-by: Moritz Fischer >> --- >> .../devicetree/bindings/reset/zynq-reset.txt | 68 ++++++++++++++++++++++ >> 1 file changed, 68 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt >> new file mode 100644 >> index 0000000..498c037a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt >> @@ -0,0 +1,68 @@ >> +Xilinx Zynq Reset Manager >> + >> +The Zynq AP-SoC has several different resets. >> + >> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. >> + >> +Required properties: >> +- compatible: "xlnx,zynq-reset" >> +- reg: SLCR offset and size taken via syscon <0x200 0x48> >> +- syscon: <&slcr> >> + This should be a phandle to the Zynq's SLCR register. > > ^ register singular? > > I still think the syscon phandle property is superfluous, > but I'm fine with keeping it for consistency. > It could always be made optional later. Great. Philipp: I expect you want to take at least 1/4 and 3/4 via your tree. I am fine if you also want to add 2/4 and 4/4 via your tree. If you think that they should go via arm-soc please let me know and I will add them to the queue. Thanks, Michal From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932581AbbHDITP (ORCPT ); Tue, 4 Aug 2015 04:19:15 -0400 Received: from mail-bl2on0093.outbound.protection.outlook.com ([65.55.169.93]:53888 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932449AbbHDITJ (ORCPT ); Tue, 4 Aug 2015 04:19:09 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; pengutronix.de; dkim=none (message not signed) header.d=none; Subject: Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. References: <1438305237-18497-1-git-send-email-moritz.fischer@ettus.com> <1438305237-18497-2-git-send-email-moritz.fischer@ettus.com> <1438675772.3793.18.camel@pengutronix.de> To: Philipp Zabel , Moritz Fischer CC: , , , , , , , , , , From: Michal Simek Message-ID: <55C0756E.8050003@xilinx.com> Date: Tue, 4 Aug 2015 10:18:54 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 MIME-Version: 1.0 In-Reply-To: <1438675772.3793.18.camel@pengutronix.de> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-21722.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BY2FFO11FD015;1:G9jS8QUFIa1DOhSWOpd6pG4h3AiKFc2ObwekJbaoqybaNNNVuXZFsvCt+QKhkfeD8LZmj9jzurI3tPBL3yCCdFn5PtCwOWq4OOFWzQt121aD2sOADi1VdcUiBhuaQkuSUF+aBN3wnlwWKA2BSIYFujCZRLi+lMfkxsyfTAtACBRNHwV07SSnWT49wzyQnNEDEI9wVHaL+CLKkH0ABg1BhmWB3WBKM708ONDa4aaONK/1s82MBGvtW4wCdAfAD5yeLfnazee+qUH34DU17QRiOA== X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(24454002)(377454003)(199003)(164054003)(479174004)(81156007)(54356999)(4001540100001)(87266999)(50986999)(76176999)(4001350100001)(5001770100001)(5001830100001)(83506001)(65816999)(86362001)(50466002)(59896002)(36386004)(6806004)(2950100001)(87936001)(33656002)(80316001)(19580405001)(19580395003)(46102003)(64706001)(106466001)(65956001)(65806001)(47776003)(77156002)(62966003)(63266004)(77096005)(64126003)(189998001)(36756003)(23746002)(5001960100002)(107886002)(92566002)(5001860100001)(107986001)(4001430100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BY2FFO11HUB023;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; 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Great. Philipp: I expect you want to take at least 1/4 and 3/4 via your tree. I am fine if you also want to add 2/4 and 4/4 via your tree. If you think that they should go via arm-soc please let me know and I will add them to the queue. Thanks, Michal