From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Date: Tue, 4 Aug 2015 21:13:28 +0530 Message-ID: <55C0DDA0.1020304@ti.com> References: <1437140844-6032-1-git-send-email-rogerq@ti.com> <1437140844-6032-3-git-send-email-rogerq@ti.com> <55C0757D.1090306@ti.com> <20150804084151.GS16878@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20150804084151.GS16878@atomide.com> Sender: linux-kernel-owner@vger.kernel.org To: Tony Lindgren , Roger Quadros Cc: nm@ti.com, nsekhar@ti.com, balbi@ti.com, grygorii.strashko@ti.com, t-kristo@ti.com, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-omap@vger.kernel.org On Tuesday 04 August 2015 02:11 PM, Tony Lindgren wrote: > * Roger Quadros [150804 01:22]: >> Tony, >> >> On 17/07/15 16:47, Roger Quadros wrote: >>> This register is required to be passed to the SATA PHY driver >>> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). >>> >>> Signed-off-by: Roger Quadros >> >> Can you please Ack or pick this for -fixes. >> Kishon has already picked patch 1 in this series. Thanks. > > Best that Kishon takes both then: > > Acked-by: Tony Lindgren merged, thanks. -Kishon > >>> --- >>> arch/arm/boot/dts/dra7.dtsi | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >>> index 8f1e25b..4a0718c 100644 >>> --- a/arch/arm/boot/dts/dra7.dtsi >>> +++ b/arch/arm/boot/dts/dra7.dtsi >>> @@ -1140,6 +1140,7 @@ >>> ctrl-module = <&omap_control_sata>; >>> clocks = <&sys_clkin1>, <&sata_ref_clk>; >>> clock-names = "sysclk", "refclk"; >>> + syscon-pllreset = <&scm_conf 0x3fc>; >>> #phy-cells = <0>; >>> }; >>> >>> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753334AbbHDPnl (ORCPT ); Tue, 4 Aug 2015 11:43:41 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:45090 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751922AbbHDPnj (ORCPT ); Tue, 4 Aug 2015 11:43:39 -0400 Message-ID: <55C0DDA0.1020304@ti.com> Date: Tue, 4 Aug 2015 21:13:28 +0530 From: Kishon Vijay Abraham I User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: Tony Lindgren , Roger Quadros CC: , , , , , , Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY References: <1437140844-6032-1-git-send-email-rogerq@ti.com> <1437140844-6032-3-git-send-email-rogerq@ti.com> <55C0757D.1090306@ti.com> <20150804084151.GS16878@atomide.com> In-Reply-To: <20150804084151.GS16878@atomide.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 04 August 2015 02:11 PM, Tony Lindgren wrote: > * Roger Quadros [150804 01:22]: >> Tony, >> >> On 17/07/15 16:47, Roger Quadros wrote: >>> This register is required to be passed to the SATA PHY driver >>> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). >>> >>> Signed-off-by: Roger Quadros >> >> Can you please Ack or pick this for -fixes. >> Kishon has already picked patch 1 in this series. Thanks. > > Best that Kishon takes both then: > > Acked-by: Tony Lindgren merged, thanks. -Kishon > >>> --- >>> arch/arm/boot/dts/dra7.dtsi | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >>> index 8f1e25b..4a0718c 100644 >>> --- a/arch/arm/boot/dts/dra7.dtsi >>> +++ b/arch/arm/boot/dts/dra7.dtsi >>> @@ -1140,6 +1140,7 @@ >>> ctrl-module = <&omap_control_sata>; >>> clocks = <&sys_clkin1>, <&sata_ref_clk>; >>> clock-names = "sysclk", "refclk"; >>> + syscon-pllreset = <&scm_conf 0x3fc>; >>> #phy-cells = <0>; >>> }; >>> >>>