diff for duplicates of <55C1E84A.9050501@rock-chips.com> diff --git a/a/1.txt b/N1/1.txt index 0d28bb5..6827cc2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ -On 08/05/2015 06:51 AM, Heiko Stübner wrote: +On 08/05/2015 06:51 AM, Heiko St?bner wrote: > Currently the stabilization thresholds for the oscillator and external pmu > are statically set to 30ms based on a 32kHz clock rate. This leaves out the > case when we don't switch to the 32kHz clock when only entering the shallow @@ -11,8 +11,8 @@ On 08/05/2015 06:51 AM, Heiko Stübner wrote: > stabilization to 0 if it is kept running during suspend, as it of course > does not need to stabilize then. > -> Reported-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> -> Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> +> Reported-by: Chris Zhong <zyw@rock-chips.com> +> Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > changes since v2: > - describe 32kHz vs 24MHz @@ -89,5 +89,5 @@ On 08/05/2015 06:51 AM, Heiko Stübner wrote: > enum rk3288_pwr_mode_con { > PMU_PWR_MODE_EN = 0, > PMU_CLK_CORE_SRC_GATE_EN, -Reviewed-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> -Tested-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +Reviewed-by: Chris Zhong <zyw@rock-chips.com> +Tested-by: Chris Zhong <zyw@rock-chips.com> diff --git a/a/content_digest b/N1/content_digest index eec4dbb..6e4509f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,14 @@ "ref\02128609.Kb18M8K28F@diego\0" "ref\01709899.JJDRtF09u7@diego\0" - "From\0Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" - "Subject\0Re: [PATCH v3 2/3] ARM: rockchip: set correct stabilization thresholds in suspend\0" + "From\0zyw@rock-chips.com (Chris Zhong)\0" + "Subject\0[PATCH v3 2/3] ARM: rockchip: set correct stabilization thresholds in suspend\0" "Date\0Wed, 05 Aug 2015 18:41:14 +0800\0" - "To\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>" - " linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" - "Cc\0Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>" - dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - " amstan-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" "\n" - "On 08/05/2015 06:51 AM, Heiko St\303\274bner wrote:\n" + "On 08/05/2015 06:51 AM, Heiko St?bner wrote:\n" "> Currently the stabilization thresholds for the oscillator and external pmu\n" "> are statically set to 30ms based on a 32kHz clock rate. This leaves out the\n" "> case when we don't switch to the 32kHz clock when only entering the shallow\n" @@ -24,8 +19,8 @@ "> stabilization to 0 if it is kept running during suspend, as it of course\n" "> does not need to stabilize then.\n" ">\n" - "> Reported-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" - "> Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "> Reported-by: Chris Zhong <zyw@rock-chips.com>\n" + "> Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" "> ---\n" "> changes since v2:\n" "> - describe 32kHz vs 24MHz\n" @@ -102,7 +97,7 @@ "> enum rk3288_pwr_mode_con {\n" "> \tPMU_PWR_MODE_EN = 0,\n" "> \tPMU_CLK_CORE_SRC_GATE_EN,\n" - "Reviewed-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" - Tested-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + "Reviewed-by: Chris Zhong <zyw@rock-chips.com>\n" + Tested-by: Chris Zhong <zyw@rock-chips.com> -2efbc5def0ed9668fdeace273a83be74e49b5544218e6b69db73dbfc2ddba8d1 +bfb6f231bda117f754a26d2c1fbebe3f61ca775eed8e2130e8a1c4cd8009b493
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