[U-Boot] [PATCH 16/28] ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4

[Dinh Nguyen <dinguyen@opensource.altera.com>]

On 8/1/15 4:34 PM, Marek Vasut wrote:
> Merge sdr_set_*() functions which are just setting registers among
> the sea of register setting in sdram_mmr_init_full(). There is no
> need to keep them separate this way, there is nothing special about
> them.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
>  drivers/ddr/altera/sdram.c | 98 +++++++++++++++++-----------------------------
>  1 file changed, 36 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
> index 595f2a4..199e8b8 100644
> --- a/drivers/ddr/altera/sdram.c
> +++ b/drivers/ddr/altera/sdram.c
> @@ -501,24 +501,6 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
>  	writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
>  }
>

<snip>

> @@ -586,7 +530,22 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
>  	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
>  
>  	set_sdr_ctrlcfg(cfg);
> -	set_sdr_dram_timing(cfg);
> +
> +	debug("Configuring DRAMTIMING1\n");
> +	writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
> +
> +	debug("Configuring DRAMTIMING2\n");
> +	writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
> +
> +	debug("Configuring DRAMTIMING3\n");
> +	writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
> +
> +	debug("Configuring DRAMTIMING4\n");
> +	writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
> +
> +	debug("Configuring LOWPWRTIMING\n");
> +	writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
> +

I don't think we need all of these debug prints?

Dinh