Re: [PATCH] drm/i915: Use masked write for Context Status Buffer Pointer

From: Michel Thierry <michel.thierry@intel.com>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Use masked write for Context Status Buffer Pointer
Date: Thu, 6 Aug 2015 15:25:55 +0100	[thread overview]
Message-ID: <55C36E73.6040306@intel.com> (raw)
In-Reply-To: <1438869659-12561-1-git-send-email-mika.kuoppala@intel.com>

On 8/6/2015 3:00 PM, Mika Kuoppala wrote:
> This register needs to be updated with masked writes.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 99bba8e..29347e7 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -521,7 +521,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
>          ring->next_context_status_buffer = write_pointer % 6;
>
>          I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
> -                  ((u32)ring->next_context_status_buffer & 0x07) << 8);
> +                  _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8));
>   }
>
>   static int execlists_context_queue(struct drm_i915_gem_request *request)
> --
> 2.1.4
>

bspec agrees... but I remember seeing these bits being written without 
the mask in gen8.

Reviewed-by: Michel Thierry <michel.thierry@intel.com>
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