From mboxrd@z Thu Jan 1 00:00:00 1970 From: Caesar Wang Subject: Re: [PATCH] thermal: rockhip: fix setting thermal shutdown polarity Date: Mon, 10 Aug 2015 14:34:57 +0800 Message-ID: <55C84611.10904@rock-chips.com> References: <20150807210052.GA34032@dtor-ws> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20150807210052.GA34032@dtor-ws> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Dmitry Torokhov , Heiko Stuebner Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Eduardo Valentin , linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org 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List-Id: linux-arm-kernel.lists.infradead.org Dear Dmitry, Thanks to work for it. ? 2015?08?08? 05:00, Dmitry Torokhov ??: > When requested thermal shutdown signal polarity is low we need to make > sure that the bit representing high level of signal is reset, and not > set all other bits in that register. > > Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better > reflect its nature. > > Signed-off-by: Dmitry Torokhov Acked-by: Caesar Wang -- Thanks, Caesar > --- > drivers/thermal/rockchip_thermal.c | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c > index 93ee307..4d5b7d4 100644 > --- a/drivers/thermal/rockchip_thermal.c > +++ b/drivers/thermal/rockchip_thermal.c > @@ -106,16 +106,14 @@ struct rockchip_thermal_data { > #define TSADCV2_AUTO_PERIOD_HT 0x6c > > #define TSADCV2_AUTO_EN BIT(0) > -#define TSADCV2_AUTO_DISABLE ~BIT(0) > #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) > #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) > -#define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8) > > #define TSADCV2_INT_SRC_EN(chn) BIT(chn) > #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) > #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) > > -#define TSADCV2_INT_PD_CLEAR ~BIT(8) > +#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) > > #define TSADCV2_DATA_MASK 0xfff > #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 > @@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs, > enum tshut_polarity tshut_polarity) > { > if (tshut_polarity == TSHUT_HIGH_ACTIVE) > - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH), > + writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, > regs + TSADCV2_AUTO_CON); > else > - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW), > + writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, > regs + TSADCV2_AUTO_CON); > > writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); > @@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs) > u32 val; > > val = readl_relaxed(regs + TSADCV2_INT_PD); > - writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD); > + writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); > } > > static void rk_tsadcv2_control(void __iomem *regs, bool enable) From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753482AbbHJGpX (ORCPT ); Mon, 10 Aug 2015 02:45:23 -0400 Received: from regular1.263xmail.com ([211.150.99.134]:40343 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753007AbbHJGpV (ORCPT ); Mon, 10 Aug 2015 02:45:21 -0400 X-Greylist: delayed 377 seconds by postgrey-1.27 at vger.kernel.org; Mon, 10 Aug 2015 02:37:53 EDT X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: wxt@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: wxt@rock-chips.com X-UNIQUE-TAG: <09c8a536b7d4c1b75124c01554891636> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <55C84611.10904@rock-chips.com> Date: Mon, 10 Aug 2015 14:34:57 +0800 From: Caesar Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Dmitry Torokhov , Heiko Stuebner CC: Eduardo Valentin , dianders@chromium.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] thermal: rockhip: fix setting thermal shutdown polarity References: <20150807210052.GA34032@dtor-ws> In-Reply-To: <20150807210052.GA34032@dtor-ws> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Dmitry, Thanks to work for it. 在 2015年08月08日 05:00, Dmitry Torokhov 写道: > When requested thermal shutdown signal polarity is low we need to make > sure that the bit representing high level of signal is reset, and not > set all other bits in that register. > > Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better > reflect its nature. > > Signed-off-by: Dmitry Torokhov Acked-by: Caesar Wang -- Thanks, Caesar > --- > drivers/thermal/rockchip_thermal.c | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c > index 93ee307..4d5b7d4 100644 > --- a/drivers/thermal/rockchip_thermal.c > +++ b/drivers/thermal/rockchip_thermal.c > @@ -106,16 +106,14 @@ struct rockchip_thermal_data { > #define TSADCV2_AUTO_PERIOD_HT 0x6c > > #define TSADCV2_AUTO_EN BIT(0) > -#define TSADCV2_AUTO_DISABLE ~BIT(0) > #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) > #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) > -#define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8) > > #define TSADCV2_INT_SRC_EN(chn) BIT(chn) > #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) > #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) > > -#define TSADCV2_INT_PD_CLEAR ~BIT(8) > +#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) > > #define TSADCV2_DATA_MASK 0xfff > #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 > @@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs, > enum tshut_polarity tshut_polarity) > { > if (tshut_polarity == TSHUT_HIGH_ACTIVE) > - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH), > + writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, > regs + TSADCV2_AUTO_CON); > else > - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW), > + writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, > regs + TSADCV2_AUTO_CON); > > writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); > @@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs) > u32 val; > > val = readl_relaxed(regs + TSADCV2_INT_PD); > - writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD); > + writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); > } > > static void rk_tsadcv2_control(void __iomem *regs, bool enable)