From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shunqian Zheng Subject: Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse Date: Tue, 11 Aug 2015 15:43:38 +0800 Message-ID: <55C9A7AA.2020905@rock-chips.com> References: <1439273706-28274-1-git-send-email-zhengsq@rock-chips.com> <1439273706-28274-2-git-send-email-zhengsq@rock-chips.com> <1757784.jPpHQAb5oi@diego> <15314033.JtZG8yr7WE@diego> Reply-To: zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <15314033.JtZG8yr7WE@diego> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, 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Zm8vbGludXgtcm9ja2NoaXAK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755226AbbHKHof (ORCPT ); Tue, 11 Aug 2015 03:44:35 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:40890 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752978AbbHKHoe (ORCPT ); Tue, 11 Aug 2015 03:44:34 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengsq@rock-chips.com X-FST-TO: xjq@rock-chips.com X-SENDER-IP: 172.245.164.6 X-LOGIN-NAME: zhengsq@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <55C9A7AA.2020905@rock-chips.com> Date: Tue, 11 Aug 2015 15:43:38 +0800 From: Shunqian Zheng Reply-To: zhengsq@rock-chips.com User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= CC: gregkh@linuxfoundation.org, srinivas.kandagatla@linaro.org, maxime.ripard@free-electrons.com, caesar.wang@rock-chips.com, dianders@chromium.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xjq@rock-chips.com Subject: Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse References: <1439273706-28274-1-git-send-email-zhengsq@rock-chips.com> <1439273706-28274-2-git-send-email-zhengsq@rock-chips.com> <1757784.jPpHQAb5oi@diego> <15314033.JtZG8yr7WE@diego> In-Reply-To: <15314033.JtZG8yr7WE@diego> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Heiko, On 2015年08月11日 15:22, Heiko Stübner wrote: > Am Dienstag, 11. August 2015, 09:16:32 schrieb Heiko Stübner: >> Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng: >>> From: ZhengShunQian >>> >>> The clock id is necessary item, changing it from 0 >>> then can be referred in driver and device tree. >>> >>> Signed-off-by: ZhengShunQian >> Reviewed-by: Heiko Stuebner >> >> >> Patch is missing the clock maintainers and list >> Mike Turquette >> Stephen Boyd >> linux-clk@vger.kernel.org I will re-send this patch and cc to clock maintainers later... >> >>> --- >>> >>> drivers/clk/rockchip/clk-rk3288.c | 2 +- >>> include/dt-bindings/clock/rk3288-cru.h | 1 + >>> 2 files changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/rockchip/clk-rk3288.c >>> b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644 >>> --- a/drivers/clk/rockchip/clk-rk3288.c >>> +++ b/drivers/clk/rockchip/clk-rk3288.c >>> @@ -647,7 +647,7 @@ static struct rockchip_clk_branch >>> rk3288_clk_branches[] >>> __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, >>> RK3288_CLKGATE_CON(11), 2, GFLAGS), >> out of curiosity, as I haven't found anything about it yet, do you also know >> what the pclk_efuse_1024 is used for? > ok, found this myself (the 32x32 bit efuse), but it looks like there is also a > clock "acc_efuse" - what is this used for? Sorry, I have not idea too.. > > > Heiko > >>> GATE(PCLK_TZPC, "pclk_tzpc", >>> "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2, >>> "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), - > GATE(0, >>> "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), >>> + GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, >>> RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm", >>> "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), >>> >>> /* ddrctrl [DDR Controller PHY clock] gates */ >>> >>> diff --git a/include/dt-bindings/clock/rk3288-cru.h >>> b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644 >>> --- a/include/dt-bindings/clock/rk3288-cru.h >>> +++ b/include/dt-bindings/clock/rk3288-cru.h >>> @@ -164,6 +164,7 @@ >>> >>> #define PCLK_DDRUPCTL1 366 >>> #define PCLK_PUBL1 367 >>> #define PCLK_WDT 368 >>> >>> +#define PCLK_EFUSE256 369 >>> >>> /* hclk gates */ >>> #define HCLK_GPS 448 > > >