From: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] Revert "drm/i915: Add eDP intermediate frequencies for CHV"
Date: Wed, 12 Aug 2015 17:31:55 +0530 [thread overview]
Message-ID: <55CB35B3.8020509@intel.com> (raw)
In-Reply-To: <20150812113218.GU5176@intel.com>
On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
> On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
>> From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@intel.com>
>>
>> This reverts
>> commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
>> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Date: Thu Mar 12 17:10:38 2015 +0200
>>
>> CHV does not support intermediate frequencies so reverting the
>> patch that added it in the first place
> My docs still say it does. Is there some undocumented problem with the
> PLL or is this just a marketing decision?
I don't think so, i too have just one document that shows the phy values
for each of
the link rates but have not found any where else to say it is supported .
Also this is not tested by anyone including us from product team so i
highly doubt
it will even work.
regarding HBR2, it was supposed to land on a future stepping that never
happened
so it is not supported at all.
>> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 6 ------
>> 1 file changed, 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 44f8a32..d9fb7a8 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -95,9 +95,6 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> 324000, 432000, 540000 };
>> static const int skl_rates[] = { 162000, 216000, 270000,
>> 324000, 432000, 540000 };
>> -static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>> - 243000, 270000, 324000, 405000,
>> - 420000, 432000, 540000 };
>> static const int default_rates[] = { 162000, 270000, 540000 };
>>
>> /**
>> @@ -1185,9 +1182,6 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>> } else if (IS_SKYLAKE(dev)) {
>> *source_rates = skl_rates;
>> return ARRAY_SIZE(skl_rates);
>> - } else if (IS_CHERRYVIEW(dev)) {
>> - *source_rates = chv_rates;
>> - return ARRAY_SIZE(chv_rates);
>> }
>>
>> *source_rates = default_rates;
>> --
>> 1.7.9.5
--
regards,
Sivakumar
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next prev parent reply other threads:[~2015-08-12 12:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-31 6:02 [PATCH 1/2] Revert "drm/i915: Add eDP intermediate frequencies for CHV" Sivakumar Thulasimani
2015-07-31 6:02 ` [PATCH 2/2] drm/i915: remove HBR2 from chv supported list Sivakumar Thulasimani
2015-08-12 13:12 ` Ville Syrjälä
2015-08-12 6:13 ` [PATCH 1/2] Revert "drm/i915: Add eDP intermediate frequencies for CHV" Sivakumar Thulasimani
2015-08-12 11:32 ` Ville Syrjälä
2015-08-12 12:01 ` Sivakumar Thulasimani [this message]
2015-08-12 13:02 ` Ville Syrjälä
2015-08-12 13:49 ` Daniel Vetter
2015-08-14 6:59 ` Jani Nikula
2015-08-14 7:31 ` Sivakumar Thulasimani
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