From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: KVM Live migration with GICv3
Date: Wed, 12 Aug 2015 17:34:25 +0100
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To: Vijay Kilari <vijay.kilari@gmail.com>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>, =?windows-1252?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, p.fedin@samsung.com
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On 11/08/15 06:25, Vijay Kilari wrote:
> Hi,
> 
>    I have prototyped Live migration with GICv3.
> For this I have made following changes
> 
> 1) Save and Restore of GICv3 registers in QEMU.
>     - For GICv2, QEMU is saving/restoring GICD, GICC  registers. For GICv3,
>      we have to save/restore GICD, GICR and ICC registers.
>      However ICC registers are system registers which cannot be
> accessed @ EL0 level (SRE=1). So these ICC registers should be
> accessed as mmio registers by QEMU, for this we have to add ioctl to
> access ICC @ EL1 level similar to GICC registers of GICv2.

I've already replied to this. The ICC_* registers *must* be exposed as
system registers. There is no GICC_* state to save. And I don't get your
EL0 access thing.

> 
> 2) KVM ioctls in kernel provides only 32-bit register access to GIC
> registers, where
>    as some registers in GICD/GICR requires 64-bit register access. I
> propose to use mmio.flag to specify 32/64 bit access.

I don't believe the MMIO registers *require* 64bit access. The spec says:

"For the GITS_*, GICD_* and GICR_* registers, the upper 32 bits and the
lower 32 bits can be accessed independently, unless the register
requires a 64 bit access."

and as far as I can see, no register mandates a 64bit access.

> 
> 3) KVM ioctls to access ICC registers for GICv3
> 
> Please provide your initial feedback. Let me know if some of this
> issues are already fixed
> 
> I am attending KVM-forum next week @ Seattle. We can discuss there as well.

Feel free to come and talk to us.

	M.
-- 
Jazz is not dead. It just smells funny...