[U-Boot] [PATCH] mxs_ocotp: Shift the HBUS divider correctly

[Stefano Babic <sbabic@denx.de>]

On 12/07/2015 15:00, Marek Vasut wrote:
> From: Chris Smith <chris@zxdesign.info>
> 
> When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk()
> for the purpose or restoring it back later, the value is not shifted by the
> HBUS divider offset in that register. This is not a problem, since the shift
> is zero on all MXS hardware. Add the shift anyway, for completeness and in
> case FSL ever decides to re-use this driver on future designs.
> 
> Signed-off-by: Chris Smith <chris@zxdesign.info>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  drivers/misc/mxs_ocotp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
> index 6f0a1d3..6c0d247 100644
> --- a/drivers/misc/mxs_ocotp.c
> +++ b/drivers/misc/mxs_ocotp.c
> @@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
>  		/* Return the original HCLK clock speed. */
>  		*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
>  		*val &= CLKCTRL_HBUS_DIV_MASK;
> +		*val >>= CLKCTRL_HBUS_DIV_OFFSET;
>  
>  		/* Scale the HCLK to 454/19 = 23.9 MHz . */
>  		scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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