From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: Design doc of adding ACPI support for arm64 on Xen - version 2 Date: Thu, 13 Aug 2015 11:40:42 +0100 Message-ID: <55CC742A.7090705@citrix.com> References: <55C413D5.7000709@huawei.com> <55CB861F020000780009A3E9@prv-mh.provo.novell.com> <55CB895E020000780009A462@prv-mh.provo.novell.com> <55CB71E1.8040309@citrix.com> <55CC582D020000780009A712@prv-mh.provo.novell.com> <1439456749.23981.24.camel@citrix.com> <55CC7D84020000780009A85C@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55CC7D84020000780009A85C@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich , Ian Campbell Cc: Hangaohuai , "Huangpeng (Peter)" , xen-devel , Stefano Stabellini , ShannonZhao , Shannon Zhao , ParthDixit , Christoffer Dall List-Id: xen-devel@lists.xenproject.org On 13/08/15 10:20, Jan Beulich wrote: >> BTW, IIRC x86 does modify at least one ACPI table which is the DMAR (I >> think), to hide the IOMMU from the guest? That's another table we would >> want to frob on ARM I think (or it's equivalent, which I think is IORT). > > Eliminating that hack is supposed to be on the VT-d maintainers' > TODO list(s) - Dom0 has no business looking at that table (and its > AMD counterpart already isn't being fiddled with in the same way). ARM SMMU is supporting 2 stage in order to protect the device also by the domain. At some point we will expose it to DOM0 and therefore may need to modify IORT. Regards, -- Julien Grall