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Date: Thu, 13 Aug 2015 14:12:04 +0100
From: Leon Alrae <leon.alrae@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH v7 04/11] target-mips: improve exception
	handling
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To: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>, qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, rth7680@gmail.com, agraf@suse.de, aurelien@aurel32.net

On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
> @@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
>  #if defined(TARGET_MIPS64)
>      case OPC_SCD:
>      case R6_OPC_SCD:
> -        save_cpu_state(ctx, 1);
>          op_st_scd(t1, t0, rt, ctx);
>          opn = "scd";
>          break;
>  #endif
>      case OPC_SC:
>      case R6_OPC_SC:
> -        save_cpu_state(ctx, 1);
>          op_st_sc(t1, t0, rt, ctx);
>          opn = "sc";
>          break;

Wouldn't we be better off assuming that conditional stores in linux-user
always take an exception (we generate fake EXCP_SC exception) and avoid
retranslation? After applying these changes I observed significant impact on
performance in linux-user multithreaded apps, for instance c11-atomic-exec
test before the change took just 2 seconds to finish, whereas now more than 30...

Thanks,
Leon

PS: multithreaded MIPS apps fail horribly in linux-user with this patch as
it's much more likely to get bitten by race conditions in translate-all.c. But
"translate-all.c thread-safety" patch series seem to fix it.