From: Richard Smith <smithbone@gmail.com>
To: Ed Swierk <eswierk@skyportsystems.com>,
Eduardo Habkost <ehabkost@redhat.com>
Cc: qemu-devel@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>
Subject: Re: [Qemu-devel] [PATCH for-2.5] piix: Document coreboot-specific RAM size config register
Date: Thu, 13 Aug 2015 11:30:57 -0400 [thread overview]
Message-ID: <55CCB831.2040801@gmail.com> (raw)
In-Reply-To: <CAO_EM_mNwAZEbdQVsonZ1qojWEQOP4OZDiE-we61AjxxHTsf=w@mail.gmail.com>
On 08/09/2015 09:48 PM, Ed Swierk wrote:
> References to coreboot commits: * Original commit adding code reading
> register offsets 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 to
> Intel 440bx code in coreboot:
> cb8eab482ff09ec256456312ef2d6e7710123551
I have vague recollection I may have been responsible for this but it
was so long ago. I'm having trouble finding the commits in gitweb.
When I put those hashes into the commit search at
review.coreboot.org I get not found.
--
Richard A. Smith
next prev parent reply other threads:[~2015-08-13 15:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-07 19:15 [Qemu-devel] [PATCH for-2.5] piix: Document coreboot-specific RAM size config register Eduardo Habkost
2015-08-10 1:48 ` Ed Swierk
2015-08-13 15:30 ` Richard Smith [this message]
2015-08-17 18:58 ` Eduardo Habkost
2015-08-25 9:52 ` Thomas Lamprecht
2015-08-25 9:06 ` Marcel Apfelbaum
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