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From: Dinh Nguyen <dinguyen@opensource.altera.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: socfpga: Fix delay in freeze controller
Date: Tue, 18 Aug 2015 15:27:29 -0500	[thread overview]
Message-ID: <55D39531.4050701@opensource.altera.com> (raw)
In-Reply-To: <1439247603-8990-1-git-send-email-marex@denx.de>



On 8/10/15 6:00 PM, Marek Vasut wrote:
> Based on observation, this udelay(20) was apparently too high and caused
> subsequent failure to calibrate DDR when U-Boot was compiled with certain
> toolchains. Lowering this delay fixed the problem.
> 
> Instead of permanently lowering the delay, calculate the correct delay
> based on the original comment, that is, obtain EOSC1 frequency and use
> it to calculate the precise delay.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
>  arch/arm/mach-socfpga/freeze_controller.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c
> index 0be643c..2b16795 100644
> --- a/arch/arm/mach-socfpga/freeze_controller.c
> +++ b/arch/arm/mach-socfpga/freeze_controller.c
> @@ -7,8 +7,8 @@
>  

Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Thanks,
Dinh

  reply	other threads:[~2015-08-18 20:27 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-10 23:00 [U-Boot] [PATCH] arm: socfpga: Fix delay in freeze controller Marek Vasut
2015-08-18 20:27 ` Dinh Nguyen [this message]
2015-08-18 22:06   ` Marek Vasut

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