diff for duplicates of <55DC7806.2010003@arm.com> diff --git a/a/1.txt b/N1/1.txt index d41aa77..747b837 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -18,7 +18,7 @@ On 25/08/15 15:04, Leo Yan wrote: >> above memory regions are in DDR as per the memory node. > > i'm not sure if understand correctly for your question; Hikey board -> has DDR 1GB at 0x0, but there have some memory regions are used for MCU. +> has DDR 1GB@0x0, but there have some memory regions are used for MCU. > Ah, I misread the address range, left the leading zero and assumed they @@ -26,3 +26,7 @@ are not in DDR range. Sorry for the noise. Regards, Sudeep +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 359c8e0..a80f3f2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,30 @@ "ref\01439977055-1747-4-git-send-email-leo.yan@linaro.org\0" "ref\055DC532C.3020005@arm.com\0" "ref\020150825140450.GB28262@leoy-linaro\0" - "From\0sudeep.holla@arm.com (Sudeep Holla)\0" - "Subject\0[PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node\0" + "From\0Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node\0" "Date\0Tue, 25 Aug 2015 15:13:26 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Cc\0Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Jian Zhang <zhangjian001-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Zhenwei Wang <Zhenwei.wang-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Haoju Mo <mohaoju-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Dan Zhao <dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + kongfei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org <kongfei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Guangyue Zeng <zengguangyue-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <Pawel.Moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <Mark.Rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org> + Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + " Bintian Wang <bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" "\00:1\0" "b\0" "\n" @@ -28,13 +48,17 @@ ">> above memory regions are in DDR as per the memory node.\n" ">\n" "> i'm not sure if understand correctly for your question; Hikey board\n" - "> has DDR 1GB at 0x0, but there have some memory regions are used for MCU.\n" + "> has DDR 1GB@0x0, but there have some memory regions are used for MCU.\n" ">\n" "\n" "Ah, I misread the address range, left the leading zero and assumed they\n" "are not in DDR range. Sorry for the noise.\n" "\n" "Regards,\n" - Sudeep + "Sudeep\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -c7ed037bce18df589fb3a9c2b20114081c3e86cf5af63b3d3f9a2433cad1eb41 +2e41b8f7fb52d23806819d3b3fd03f8812973fc6e2d2d90e9d4812ab777db831
diff --git a/a/1.txt b/N2/1.txt index d41aa77..b0a1400 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -18,7 +18,7 @@ On 25/08/15 15:04, Leo Yan wrote: >> above memory regions are in DDR as per the memory node. > > i'm not sure if understand correctly for your question; Hikey board -> has DDR 1GB at 0x0, but there have some memory regions are used for MCU. +> has DDR 1GB@0x0, but there have some memory regions are used for MCU. > Ah, I misread the address range, left the leading zero and assumed they diff --git a/a/content_digest b/N2/content_digest index 359c8e0..6efb090 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,10 +2,33 @@ "ref\01439977055-1747-4-git-send-email-leo.yan@linaro.org\0" "ref\055DC532C.3020005@arm.com\0" "ref\020150825140450.GB28262@leoy-linaro\0" - "From\0sudeep.holla@arm.com (Sudeep Holla)\0" - "Subject\0[PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node\0" + "From\0Sudeep Holla <sudeep.holla@arm.com>\0" + "Subject\0Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node\0" "Date\0Tue, 25 Aug 2015 15:13:26 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Leo Yan <leo.yan@linaro.org>\0" + "Cc\0Sudeep Holla <sudeep.holla@arm.com>" + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + guodong.xu@linaro.org <guodong.xu@linaro.org> + Jian Zhang <zhangjian001@hisilicon.com> + Zhenwei Wang <Zhenwei.wang@hisilicon.com> + Haoju Mo <mohaoju@hisilicon.com> + Dan Zhao <dan.zhao@hisilicon.com> + kongfei@hisilicon.com <kongfei@hisilicon.com> + Guangyue Zeng <zengguangyue@hisilicon.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <Pawel.Moll@arm.com> + Mark Rutland <Mark.Rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + Catalin Marinas <Catalin.Marinas@arm.com> + Will Deacon <Will.Deacon@arm.com> + Jassi Brar <jassisinghbrar@gmail.com> + Bintian Wang <bintian.wang@huawei.com> + Haojian Zhuang <haojian.zhuang@linaro.org> + Yiping Xu <xuyiping@hisilicon.com> + " Wei Xu <xuwei5@hisilicon.com>\0" "\00:1\0" "b\0" "\n" @@ -28,7 +51,7 @@ ">> above memory regions are in DDR as per the memory node.\n" ">\n" "> i'm not sure if understand correctly for your question; Hikey board\n" - "> has DDR 1GB at 0x0, but there have some memory regions are used for MCU.\n" + "> has DDR 1GB@0x0, but there have some memory regions are used for MCU.\n" ">\n" "\n" "Ah, I misread the address range, left the leading zero and assumed they\n" @@ -37,4 +60,4 @@ "Regards,\n" Sudeep -c7ed037bce18df589fb3a9c2b20114081c3e86cf5af63b3d3f9a2433cad1eb41 +f6ee4c707771592d4fe2a484e5c078fab158ae59d83dd59c4ef51f03273e3fa9
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