From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
To: Alim Akhtar <alim.akhtar@samsung.com>, linux-samsung-soc@vger.kernel.org
Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org,
mturquette@baylibre.com, amit.daniel@samsung.com
Subject: Re: [PATCH v2 2/4] clk: samsung: exynos7: Fix CMU TOP1 block
Date: Wed, 26 Aug 2015 14:23:28 +0900 [thread overview]
Message-ID: <55DD4D50.70602@samsung.com> (raw)
In-Reply-To: <1440559844-12572-3-git-send-email-alim.akhtar@samsung.com>
On 26.08.2015 12:30, Alim Akhtar wrote:
> As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
> and the GATE clocks are at bit 16 in their respective registers.
> For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
> And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
> This patch corrects it.
> This also adds xxx_FSYS11 to be saved/restore during s2r cycles.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos7.c | 24 +++++++++++++++---------
> 1 file changed, 15 insertions(+), 9 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
next prev parent reply other threads:[~2015-08-26 5:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-26 3:30 [PATCH v2 0/4] Improvements on exynos7 clock Alim Akhtar
2015-08-26 3:30 ` [PATCH v2 1/4] clk: samsung: exynos7: Fix CMU TOPC block clock Alim Akhtar
2015-08-26 5:22 ` Krzysztof Kozlowski
2015-08-26 3:30 ` [PATCH v2 2/4] clk: samsung: exynos7: Fix CMU TOP1 block Alim Akhtar
2015-08-26 5:23 ` Krzysztof Kozlowski [this message]
2015-08-26 3:30 ` [PATCH v2 3/4] clk: samsung: exynos7: Correct nr_clk_ids for fsys0 Alim Akhtar
2015-08-26 3:30 ` [PATCH v2 4/4] clk: samsung: exynos7: Correct nr_clk_ids for fsys1 Alim Akhtar
2015-09-15 9:27 ` [PATCH v2 0/4] Improvements on exynos7 clock Sylwester Nawrocki
2015-09-15 9:32 ` Alim Akhtar
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