From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH V4 3/4] x86/xsaves: enable xsaves/xrstors for hvm guest Date: Wed, 26 Aug 2015 11:36:53 +0100 Message-ID: <55DD96C5.5080701@citrix.com> References: <1440500087-9852-1-git-send-email-shuai.ruan@linux.intel.com> <1440500087-9852-4-git-send-email-shuai.ruan@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1440500087-9852-4-git-send-email-shuai.ruan@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Shuai Ruan , xen-devel@lists.xen.org Cc: kevin.tian@intel.com, wei.liu2@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, eddie.dong@intel.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, jun.nakajima@intel.com, keir@xen.org List-Id: xen-devel@lists.xenproject.org On 25/08/15 11:54, Shuai Ruan wrote: > This patch enables xsaves for hvm guest, includes: > 1.handle xsaves vmcs init and vmexit. > 2.add logic to write/read the XSS msr. > > Signed-off-by: Shuai Ruan Reviewed-by: Andrew Cooper , given two corrections... > --- > xen/arch/x86/hvm/hvm.c | 43 ++++++++++++++++++++++++++++++++++++++ > xen/arch/x86/hvm/vmx/vmcs.c | 6 ++++-- > xen/arch/x86/hvm/vmx/vmx.c | 20 ++++++++++++++++++ > xen/arch/x86/xstate.c | 4 ++-- > xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++++++ > xen/include/asm-x86/hvm/vmx/vmx.h | 2 ++ > xen/include/asm-x86/xstate.h | 1 + > 7 files changed, 79 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c > index dc444ac..57612de 100644 > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -4540,6 +4540,33 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, > *ebx = _eax + _ebx; > } > } > + if ( count == 1 ) > + { > + if ( cpu_has_xsaves ) > + { > + *ebx = XSTATE_AREA_MIN_SIZE; > + if ( v->arch.xcr0 | v->arch.msr_ia32_xss ) > + for ( sub_leaf = 2; sub_leaf < 63; sub_leaf++ ) > + { > + if ( !((v->arch.xcr0 | v->arch.msr_ia32_xss) > + & (1ULL << sub_leaf)) ) Stray hard tabs. > @@ -4771,6 +4804,16 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t msr_content, > return X86EMUL_EXCEPTION; > break; > > + case MSR_IA32_XSS: > + /* > + * skylake only support bit 8 , but it is > + * not support in xen. > + */ I would alter this comment to /* No XSS features currently supported for guests. */ The skylake bits are covered by cpu_has_xsaves. ~Andrew