From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 3/3] drm/i915: Support DDI lane reversal for DP Date: Wed, 26 Aug 2015 17:39:40 +0530 Message-ID: <55DDAC84.7060105@intel.com> References: <1438099409-25456-1-git-send-email-benjamin.tissoires@redhat.com> <1438099409-25456-4-git-send-email-benjamin.tissoires@redhat.com> <55B88E25.6000006@intel.com> <20150729152240.GD2743@mail.corp.redhat.com> <55B9A471.2070107@intel.com> <20150805193427.GA6097@mail.corp.redhat.com> <20150817200653.GB14631@mail.corp.redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id D5E936EA36 for ; Wed, 26 Aug 2015 05:09:44 -0700 (PDT) In-Reply-To: <20150817200653.GB14631@mail.corp.redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Benjamin Tissoires , =?UTF-8?B?U3TDqXBo?= =?UTF-8?B?YW5lIE1hcmNoZXNpbg==?= Cc: Daniel Vetter , intel-gfx , Todd Broch , linux-kernel@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org CgpPbiA4LzE4LzIwMTUgMTozNiBBTSwgQmVuamFtaW4gVGlzc29pcmVzIHdyb3RlOgo+IE9uIEF1 ZyAxNCAyMDE1IG9yIHRoZXJlYWJvdXRzLCBTdMOpcGhhbmUgTWFyY2hlc2luIHdyb3RlOgo+PiBP biBXZWQsIEF1ZyA1LCAyMDE1IGF0IDEyOjM0IFBNLCBCZW5qYW1pbiBUaXNzb2lyZXMKPj4gPGJl bmphbWluLnRpc3NvaXJlc0ByZWRoYXQuY29tPiB3cm90ZToKPj4+IE9uIEp1bCAzMCAyMDE1IG9y IHRoZXJlYWJvdXRzLCBTaXZha3VtYXIgVGh1bGFzaW1hbmkgd3JvdGU6Cj4+Pj4KPj4+PiBPbiA3 LzI5LzIwMTUgODo1MiBQTSwgQmVuamFtaW4gVGlzc29pcmVzIHdyb3RlOgo+Pj4+PiBPbiBKdWwg MjkgMjAxNSBvciB0aGVyZWFib3V0cywgU2l2YWt1bWFyIFRodWxhc2ltYW5pIHdyb3RlOgo+Pj4+ Pj4gd2h5IG5vdCBkZXRlY3QgcmV2ZXJzZSBpbiBpbnRlbF9kcF9kZXRlY3QvaW50ZWxfaHBkX3B1 bHNlID8gdGhhdCB3YXkgeW91IGNhbgo+Pj4+Pj4gaWRlbnRpZnkgYm90aCBsYW5lIGNvdW50IGFu ZCByZXZlcnNhbCBzdGF0ZSB3aXRob3V0IHRvdWNoaW5nIGFueXRoaW5nIGluIHRoZQo+Pj4+Pj4g bGluayB0cmFpbmluZyBjb2RlLiBpIGFtIHlldCB0byB1cHN0cmVhbSBteSBjaGFuZ2VzIGZvciBD SFQgdGhhdCBpIGNhbiBzaGFyZQo+Pj4+Pj4gaWYgcmVxdWlyZWQgdGhhdCBkb2VzIHRoZSBzYW1l IGluIGludGVsX2RwX2RldGVjdCB3aXRob3V0IHRvdWNoaW5nIGFueSBsaW5lCj4+Pj4+PiBpbiBs aW5rIHRyYWluaW5nIHBhdGguCj4+Pj4+IFdpdGggbXkgY3VycmVudCBsaW1pdGVkIGtub3dsZWRn ZSBvZiB0aGUgZHAgaG90cGx1ZyAoYW5kIGk5MTUgZHJpdmVyKSBJCj4+Pj4+IGFtIG5vdCBzdXJl IHdlIGNvdWxkIGRldGVjdCB0aGUgcmV2ZXJzZWQgc3RhdGUgd2l0aG91dCB0cnlpbmcgdG8gdHJh aW4gMQo+Pj4+PiBsYW5lIG9ubHkuIEknZCBiZSBnbGFkIHRvIGxvb2sgYXQgeW91ciBjaGFuZ2Vz IGFuZCB0ZXN0IHRoZW0gb24gbXkKPj4+Pj4gc3lzdGVtIGlmIHlvdSB0aGluayB0aGF0IGNvdWxk IGhlbHAgaGF2aW5nIGEgY2xlYW5lciBzb2x1dGlvbi4KPj4+Pj4KPj4+Pj4gQ2hlZXJzLAo+Pj4+ PiBCZW5qYW1pbgo+Pj4+IE5vLCB3aGF0IGkgcmVjb21tZW5kZWQgd2FzIHRvIGRvIGxpbmsgdHJh aW5pbmcgYnV0IGluIGludGVsX2RwX2RldGVjdC4gU2luY2UKPj4+PiBVU0IgVHlwZSBDIGNhYmxl Cj4+Pj4gYWxzbyBoYXMgaXRzIG93biBsYW5lIGNvdW50IHJlc3RyaWN0aW9uIChpdCBjYW4gaGF2 ZSBkaWZmZXJlbnQgbGFuZSBjb3VudAo+Pj4+IHRoYW4gdGhlIG9uZSBzdXBwb3J0ZWQKPj4+PiBi eSBwYW5lbCkgeW91IG1pZ2h0IGhhdmUgdG8gZmlndXJlIHRoYXQgb3V0IGFzIHdlbGwuIHNvIGJv dGggcmV2ZXJzYWwgYW5kCj4+Pj4gbGFuZSBjb3VudCBkZXRlY3Rpb24KPj4+PiBjYW4gYmUgZG9u ZSBvdXRzaWRlIHRoZSBtb2Rlc2V0IHBhdGggYW5kIGtlZXAgdGhlIGNvZGUgZnJlZSBvZiB0eXBl IEMKPj4+PiBjaGFuZ2VzIG91dHNpZGUKPj4+PiBkZXRlY3Rpb24gcGF0aC4KPj4+Pgo+Pj4+IFBs ZWFzZSBmaW5kIGJlbG93IHRoZSBjb2RlIHRvIGRvIHRoZSBzYW1lLiBEbyBub3Qgd2FzdGUgdGlt ZSB0cnlpbmcgdG8gYXBwbHkKPj4+PiB0aGlzIGRpcmVjdGx5IG9uCj4+Pj4gbmlnaHRseSBzaW5j ZSB0aGlzIGlzIGJhc2VkIG9uIGEgbG9jYWwgdHJlZSBhbmQgYmVjYXVzZSB0aGlzIGlzIHByZS0g YXRvbWljCj4+Pj4gY2hhbmdlcyBjb2RlLCBzbyB5b3UKPj4+PiBtaWdodCBoYXZlIHRvIG1vZGlm eSBjaHZfdXBmcm9udF9saW5rX3RyYWluIHRvIHdvcmsgb24gdG9wIG9mIHRoZSBsYXRlc3QKPj4+ PiBuaWdodGx5IGNvZGUuIHdlCj4+Pj4gYXJlIHN1cHBvc2VkIHRvIHVwc3RyZWFtIHRoaXMgYW5k IGlzIGluIG15IHRvZG8gbGlzdC4KPj4+Pgo+Pj4gW29yaWdpbmFsIHBhdGNoIHNuaXBwZWQuLi5d Cj4+Pgo+Pj4gSGkgU2l2YWt1bWFyLAo+Pj4KPj4+IFNvIEkgbWFuYWdlZCB0byBtYW51YWxseSBy ZS1hcHBseSB5b3VyIHBhdGNoIG9uIHRvcCBvZgo+Pj4gZHJtLWludGVsLW5pZ2h0bHksIGFuZCB0 cmllZCB0byBwb3J0IGl0IHRvIG1ha2UgQnJvYWR3ZWxsIHdvcmtpbmcgdG9vLgo+Pj4gSXQgd29y a3MgT0sgaWYgdGhlIHN5c3RlbSBpcyBhbHJlYWR5IGJvb3Qgd2l0aG91dCBhbnkgZXh0ZXJuYWwg RFAgdXNlZC4KPj4+IEluIHRoaXMgY2FzZSwgdGhlIGRldGVjdGlvbiB3b3JrcyBhbmQgSSBjYW4g c2VlIG15IGV4dGVybmFsIG1vbml0b3IKPj4+IHdvcmtpbmcgcHJvcGVybHkuCj4+Pgo+Pj4gSG93 ZXZlciwgaWYgdGhlIG1vbml0b3IgaXMgY29sZCBwbHVnZ2VkLCB0aGUgY3B1L0dQVSBoYW5ncyBh bmQgSSBjYW4gbm90Cj4+PiB1bmRlcnN0YW5kIHdoeS4gSSB0aGluayBJIGVuYWJsZWQgYWxsIHRo YXQgaXMgbWVudGlvbmVkIGluIHRoZSBQUk0gdG8gYmUKPj4+IGFibGUgdG8gdHJhaW4gdGhlIERQ IGxpbmssIGJ1dCBJIGFtIG9idmlvdXNseSBtaXNzaW5nIHNvbWV0aGluZyBlbHNlLgo+Pj4gQ2Fu IHlvdSBoYXZlIGEgbG9vaz8KPj4+Cj4+IEhpIEJlbmphbWluLAo+Pgo+PiBJIHdvdWxkIHJlY29t bWVuZCBhZ2FpbnN0IHRoaXMgYXBwcm9hY2guIFNvbWUgYWRhcHRlcnMgd2lsbCBjbGFpbSB0aGF0 Cj4+IHRoZXkgcmVjb3ZlcmVkIGEgY2xvY2sgZXZlbiB3aGVuIGl0IGlzbid0IG9uIHRoZSBsYW5l cyB5b3UgZW5hYmxlZCwKPj4gd2hpY2ggbWVhbnMgdGhhdCB0aGUgcmV2ZXJzYWwgZGV0ZWN0aW9u IGRvZXNuJ3QgYWx3YXlzIHdvcmsuIFRoZSBvbmx5Cj4+IHJlbGlhYmxlIHdheSB0byBkbyB0aGlz IGlzIHRvIGdvIHRhbGsgdG8gdGhlIENocm9tZSBPUyBFQyAoeW91IGNhbgo+PiBmaW5kIHRoZXNl IHBhdGNoZXMgbGF0ZXIgaW4gdGhlIENocm9tZSBPUyB0cmVlKS4gSXQncyBub3QgYXMgZ2VuZXJp YywKPj4gYnV0IHdlIG1pZ2h0IGJlIGFibGUgdG8gYWJzdHJhY3QgdGhhdCBsb2dpYywgbWF5YmUu Cj4+Cj4gSGkgU3TDqXBoYW5lLAo+Cj4gVGhpcyBpcyBhIHZlcnkgZ29vZCBuZXdzLiBJIHdhcyBh ZnJhaWQgd2Ugd291bGQgbm90IGhhdmUgYWNjZXNzIHRvIHRoZQo+IGhhcmR3YXJlIGNvbnRyb2xs ZXIgYmVjYXVzZSB0aGUgSW50ZWwgY29udHJvbGxlciBodWIgc3BlYyB3YXMgbm90Cj4gcHVibGlj Lgo+Cj4gSSB3aWxsIHRyeSB0byBoYXZlIGEgbG9vayBhdCBpdCwgYnV0IHRoZSBsYXRlc3QgY2hy b21lb3MgYnJhbmNoICgzLjE4KQo+IHNlZW1zIHRvIGRpZmZlciBxdWl0ZSBhIGxvdCBmcm9tIHRo ZSB1cHN0cmVhbSBvbmUuIEFueXdheSwgZmluZ2Vycwo+IGNyb3NzZWQuCj4KPiBDaGVlcnMsCj4g QmVuamFtaW4KSGkgQmVuamFtaW4vU3TDqXBoYW4sCiAgICAgQWxsIEludGVsIHBsYXRmb3JtcyAo YXQtbGVhc3QgdGhvc2UgaSBpbnF1aXJlZCBhYm91dCkgaGFuZGxlIGxhbmUgCnJldmVyc2FsIGlu IEhXLgp5b3VyIHN0YXRlbWVudCB0aGF0IGxpbmsgdHJhaW5pbmcgd2lsbCBwYXNzIGV2ZW4gb24g cmV2ZXJzZWQgbGFuZSBzZWVtcyAKdG8gcG9pbnQKdG8gdGhlIHNhbWUgZmFjdC4gaW4gc3VjaCBh IHNjZW5hcmlvIHdoeSBzaG91bGQgdGhlIGVuY29kZXIvY29ubmVjdG9yIGNhcmUKaWYgdGhlIGxh bmUgaXMgcmV2ZXJzZWQgb3Igbm90ID8KCi0tIApyZWdhcmRzLApTaXZha3VtYXIKCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5n IGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRl c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756760AbbHZMJr (ORCPT ); Wed, 26 Aug 2015 08:09:47 -0400 Received: from mga01.intel.com ([192.55.52.88]:17038 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751887AbbHZMJp (ORCPT ); Wed, 26 Aug 2015 08:09:45 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,415,1437462000"; d="scan'208";a="548841186" Message-ID: <55DDAC84.7060105@intel.com> Date: Wed, 26 Aug 2015 17:39:40 +0530 From: Sivakumar Thulasimani User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Benjamin Tissoires , =?UTF-8?B?U3TDqXBo?= =?UTF-8?B?YW5lIE1hcmNoZXNpbg==?= CC: Daniel Vetter , intel-gfx , Todd Broch , linux-kernel@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP References: <1438099409-25456-1-git-send-email-benjamin.tissoires@redhat.com> <1438099409-25456-4-git-send-email-benjamin.tissoires@redhat.com> <55B88E25.6000006@intel.com> <20150729152240.GD2743@mail.corp.redhat.com> <55B9A471.2070107@intel.com> <20150805193427.GA6097@mail.corp.redhat.com> <20150817200653.GB14631@mail.corp.redhat.com> In-Reply-To: <20150817200653.GB14631@mail.corp.redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/18/2015 1:36 AM, Benjamin Tissoires wrote: > On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote: >> On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires >> wrote: >>> On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote: >>>> >>>> On 7/29/2015 8:52 PM, Benjamin Tissoires wrote: >>>>> On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote: >>>>>> why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you can >>>>>> identify both lane count and reversal state without touching anything in the >>>>>> link training code. i am yet to upstream my changes for CHT that i can share >>>>>> if required that does the same in intel_dp_detect without touching any line >>>>>> in link training path. >>>>> With my current limited knowledge of the dp hotplug (and i915 driver) I >>>>> am not sure we could detect the reversed state without trying to train 1 >>>>> lane only. I'd be glad to look at your changes and test them on my >>>>> system if you think that could help having a cleaner solution. >>>>> >>>>> Cheers, >>>>> Benjamin >>>> No, what i recommended was to do link training but in intel_dp_detect. Since >>>> USB Type C cable >>>> also has its own lane count restriction (it can have different lane count >>>> than the one supported >>>> by panel) you might have to figure that out as well. so both reversal and >>>> lane count detection >>>> can be done outside the modeset path and keep the code free of type C >>>> changes outside >>>> detection path. >>>> >>>> Please find below the code to do the same. Do not waste time trying to apply >>>> this directly on >>>> nightly since this is based on a local tree and because this is pre- atomic >>>> changes code, so you >>>> might have to modify chv_upfront_link_train to work on top of the latest >>>> nightly code. we >>>> are supposed to upstream this and is in my todo list. >>>> >>> [original patch snipped...] >>> >>> Hi Sivakumar, >>> >>> So I managed to manually re-apply your patch on top of >>> drm-intel-nightly, and tried to port it to make Broadwell working too. >>> It works OK if the system is already boot without any external DP used. >>> In this case, the detection works and I can see my external monitor >>> working properly. >>> >>> However, if the monitor is cold plugged, the cpu/GPU hangs and I can not >>> understand why. I think I enabled all that is mentioned in the PRM to be >>> able to train the DP link, but I am obviously missing something else. >>> Can you have a look? >>> >> Hi Benjamin, >> >> I would recommend against this approach. Some adapters will claim that >> they recovered a clock even when it isn't on the lanes you enabled, >> which means that the reversal detection doesn't always work. The only >> reliable way to do this is to go talk to the Chrome OS EC (you can >> find these patches later in the Chrome OS tree). It's not as generic, >> but we might be able to abstract that logic, maybe. >> > Hi Stéphane, > > This is a very good news. I was afraid we would not have access to the > hardware controller because the Intel controller hub spec was not > public. > > I will try to have a look at it, but the latest chromeos branch (3.18) > seems to differ quite a lot from the upstream one. Anyway, fingers > crossed. > > Cheers, > Benjamin Hi Benjamin/Stéphan, All Intel platforms (at-least those i inquired about) handle lane reversal in HW. your statement that link training will pass even on reversed lane seems to point to the same fact. in such a scenario why should the encoder/connector care if the lane is reversed or not ? -- regards, Sivakumar