Re: [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

[Clint Taylor <clinton.a.taylor@intel.com>]

On 08/26/2015 12:58 AM, Jani Nikula wrote:
> Make it available outside of intel_dp.c.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_dp.c      | 34 ----------------------------------
>   drivers/gpu/drm/i915/intel_drv.h     |  1 +
>   3 files changed, 34 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cba6299b3450..f25a847bcbc5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -135,6 +135,39 @@ intel_pch_rawclk(struct drm_device *dev)
>   	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
>   }
>
> +/* hrawclock is 1/4 the FSB frequency */
> +int intel_hrawclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t clkcfg;
> +
> +	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
> +	if (IS_VALLEYVIEW(dev))
> +		return 200;
> +
> +	clkcfg = I915_READ(CLKCFG);
> +	switch (clkcfg & CLKCFG_FSB_MASK) {
> +	case CLKCFG_FSB_400:
> +		return 100;
> +	case CLKCFG_FSB_533:
> +		return 133;
> +	case CLKCFG_FSB_667:
> +		return 166;
> +	case CLKCFG_FSB_800:
> +		return 200;
> +	case CLKCFG_FSB_1067:
> +		return 266;
> +	case CLKCFG_FSB_1333:
> +		return 333;
> +	/* these two are just a guess; one of them might be right */
> +	case CLKCFG_FSB_1600:
> +	case CLKCFG_FSB_1600_ALT:
> +		return 400;
> +	default:
> +		return 133;
> +	}
> +}
> +
>   static inline u32 /* units of 100MHz */
>   intel_fdi_link_freq(struct drm_device *dev)
>   {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 67f0e291232f..0800d87e876c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -253,40 +253,6 @@ static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
>   		dst[i] = src >> ((3-i) * 8);
>   }
>
> -/* hrawclock is 1/4 the FSB frequency */
> -static int
> -intel_hrawclk(struct drm_device *dev)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint32_t clkcfg;
> -
> -	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
> -	if (IS_VALLEYVIEW(dev))
> -		return 200;
> -
> -	clkcfg = I915_READ(CLKCFG);
> -	switch (clkcfg & CLKCFG_FSB_MASK) {
> -	case CLKCFG_FSB_400:
> -		return 100;
> -	case CLKCFG_FSB_533:
> -		return 133;
> -	case CLKCFG_FSB_667:
> -		return 166;
> -	case CLKCFG_FSB_800:
> -		return 200;
> -	case CLKCFG_FSB_1067:
> -		return 266;
> -	case CLKCFG_FSB_1333:
> -		return 333;
> -	/* these two are just a guess; one of them might be right */
> -	case CLKCFG_FSB_1600:
> -	case CLKCFG_FSB_1600_ALT:
> -		return 400;
> -	default:
> -		return 133;
> -	}
> -}
> -
>   static void
>   intel_dp_init_panel_power_sequencer(struct drm_device *dev,
>   				    struct intel_dp *intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 81b7d77a3c8b..ca475f2a5f7c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -993,6 +993,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
>   extern const struct drm_plane_funcs intel_plane_funcs;
>   bool intel_has_pending_fb_unpin(struct drm_device *dev);
>   int intel_pch_rawclk(struct drm_device *dev);
> +int intel_hrawclk(struct drm_device *dev);
>   void intel_mark_busy(struct drm_device *dev);
>   void intel_mark_idle(struct drm_device *dev);
>   void intel_crtc_restore_mode(struct drm_crtc *crtc);
>

Simple move of the function with no change in functionality.

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com>
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