Re: [Qemu-devel] [PATCH] e500 ATMU register reads broken

[Rudolf Marek <rudolf.marek@sysgo.com>]

Hi all,

 > Sorry for the long delay. Please CC qemu-ppc@nongnu.org on the next
> submission, so that more PPC people have the chance to review the patch ;).

I see, I missed this mailing list -
http://wiki.qemu.org/Contribute/SubmitAPatch

As it do not not mention it.

> Thanks, applied to ppc-next.

Thanks! Will it be part of 2.4.x ?

> Would you mind to follow up with a patch to the mpc8544ds machine file
> that programs the ATMUs on init?

I also use -kernel option.

Hm I don't know how to program it in QEMU internally, what I'm currently doing 
in my code is bellow.

The PCI_IO and PCI_MEM are the addresses of the translation windows in CPU 
space. I guess you can set them to match MPC8544ds Here is my current WIP code 
to do it:

   /* Disable all translations */
     pit[0].war = 0;
     pit[1].war = 0;
     pit[2].war = 0;

     pot[0].war = 0;
     pot[1].war = 0;
     pot[2].war = 0;
     pot[3].war = 0;
     pot[4].war = 0;
     __asm__ volatile ("eieio");

     /* setup the PCI inbound window 1:1 for first 2GB */
     pit[0].war = 0;
     pit[0].ar = 0;
     pit[0].war = 0;
     pit[0].wbear = 0;
     /* 2^31 is 2GB, it is -1 encoded as 30 */
     pit[0].war = PIWAR_EN |  PIWAR_PF | PIWAR_LOCAL |
                  PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | 30;

     /* setup the outbound translation as 1:1 256M */
     pot[1].war = 0;
     pot[1].ear = 0;
     /* 2^28 is 256M it is -1 encoded as 27 */
     pot[1].wbar = (PCI_MEM >> 12) & 0x000fffff;
     pot[1].ar = (PCI_MEM >> 12) & 0x000fffff;
     __asm__ volatile ("eieio");
     pot[1].war = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | 27;

     /* Outbound IO port window size of window is 64K */
     pot[2].war = 0;
     pot[2].ear = 0;
     pot[2].wbar = (PCI_IO >> 12) & 0x000fffff;
     pot[2].ar = 0;
     __asm__ volatile ("eieio");
     /* 2^16 is 64K it is -1 encoded as 15 */
     pot[2].war = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE | 15;

It programs the 1:1 PCI to CPU for 2GB of RAM. And it programs the PCI MMIO 
window 1:1 with start PCI_MEM size 256M and it places the i/o ports at PCI_IO.

In theory you should also enable the MEM decoder of the PCI root device, but I 
think QEMU does not need it (see u-boot what it is doing).

Feel free to use this code as a template for the QEMU support,

Thanks
Rudolf

-
S přátelským pozdravem / Best regards / Mit freundlichen Grüßen

Ing. Rudolf Marek
SYSGO s.r.o.
Zelený pruh 99
CZ-14800 Praha 4
Phone: +420 222138 111, +49 6136 9948 111
Fax: +420 296374890, +49 6136 9948 1 111
rudolf.marek@sysgo.com

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