diff for duplicates of <55E4FBE4.3010808@huawei.com> diff --git a/a/1.txt b/N1/1.txt index 7e327a2..c3742b8 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -7,8 +7,8 @@ On 2015/8/31 22:40, Leo Yan wrote: >>>> >>>> Also add dts file to support Hip05-D02 development board. >>>> ->>>> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> ->>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> +>>>> Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> +>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> >>>> --- >>>> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >>>> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ @@ -52,7 +52,7 @@ On 2015/8/31 22:40, Leo Yan wrote: >>>> + model = "Hisilicon Hip05 D02 Development Board"; >>>> + compatible = "hisilicon,hip05-d02"; >>>> + ->>>> + memory at 00000000 { +>>>> + memory@00000000 { >>>> + device_type = "memory"; >>>> + reg = <0x0 0x00000000 0x0 0x80000000>; >>>> + }; @@ -162,14 +162,14 @@ On 2015/8/31 22:40, Leo Yan wrote: >>>> + }; >>>> + }; >>>> + ->>>> + cpu0: cpu at 20000 { +>>>> + cpu0: cpu@20000 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>> >>> Change to "arm,cortex-a57","arm,armv8"? >>> >> ->> Ok?but I think should be "hisilicon,hip05","arm,armv8". +>> Ok，but I think should be "hisilicon,hip05","arm,armv8". > > If the CPU is a starndard ARM core (such like CA53, CA57, etc), you > need directly use the CPU type which has been defined in: @@ -185,4 +185,10 @@ Hip05 is the name for SoC. > Leo Yan > > . -> +> + + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 701a4c3..688f9e6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,10 +3,26 @@ "ref\020150831131244.GB6194@leoy-linaro\0" "ref\055E45A46.7040805@huawei.com\0" "ref\020150831144019.GA22491@leoy-linaro\0" - "From\0dingtianhong@huawei.com (Ding Tianhong)\0" - "Subject\0[PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" + "From\0Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" + "Subject\0Re: [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" "Date\0Tue, 1 Sep 2015 09:14:12 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Cc\0mark.rutland-5wv7dgnIgG8@public.gmane.org" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + pawel.moll-5wv7dgnIgG8@public.gmane.org + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org + marc.zyngier-5wv7dgnIgG8@public.gmane.org + catalin.marinas-5wv7dgnIgG8@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + rob.herring-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On 2015/8/31 22:40, Leo Yan wrote:\n" @@ -18,8 +34,8 @@ ">>>>\n" ">>>> Also add dts file to support Hip05-D02 development board.\n" ">>>>\n" - ">>>> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>\n" - ">>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>\n" + ">>>> Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\n" + ">>>> Signed-off-by: Kefeng Wang <wangkefeng.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\n" ">>>> ---\n" ">>>> arch/arm64/boot/dts/hisilicon/Makefile | 2 +-\n" ">>>> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++\n" @@ -63,7 +79,7 @@ ">>>> +\tmodel = \"Hisilicon Hip05 D02 Development Board\";\n" ">>>> +\tcompatible = \"hisilicon,hip05-d02\";\n" ">>>> +\n" - ">>>> +\tmemory at 00000000 {\n" + ">>>> +\tmemory@00000000 {\n" ">>>> +\t\tdevice_type = \"memory\";\n" ">>>> +\t\treg = <0x0 0x00000000 0x0 0x80000000>;\n" ">>>> +\t};\n" @@ -173,14 +189,14 @@ ">>>> +\t\t\t};\n" ">>>> +\t\t};\n" ">>>> +\n" - ">>>> +\t\tcpu0: cpu at 20000 {\n" + ">>>> +\t\tcpu0: cpu@20000 {\n" ">>>> +\t\t\tdevice_type = \"cpu\";\n" ">>>> +\t\t\tcompatible = \"arm,armv8\";\n" ">>>\n" ">>> Change to \"arm,cortex-a57\",\"arm,armv8\"?\n" ">>>\n" ">>\n" - ">> Ok?but I think should be \"hisilicon,hip05\",\"arm,armv8\".\n" + ">> Ok\357\274\214but I think should be \"hisilicon,hip05\",\"arm,armv8\".\n" "> \n" "> If the CPU is a starndard ARM core (such like CA53, CA57, etc), you\n" "> need directly use the CPU type which has been defined in:\n" @@ -196,6 +212,12 @@ "> Leo Yan\n" "> \n" "> .\n" - > + "> \n" + "\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -9cce0e5c6f9ac5768afbb27d02c7aa68863a3c84a1947957047feaa41e628af9 +b24871647aa975465b950137108668e96f41df54a8ef86ee68c7fd9c301c1904
diff --git a/a/1.txt b/N2/1.txt index 7e327a2..54c08d6 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -52,7 +52,7 @@ On 2015/8/31 22:40, Leo Yan wrote: >>>> + model = "Hisilicon Hip05 D02 Development Board"; >>>> + compatible = "hisilicon,hip05-d02"; >>>> + ->>>> + memory at 00000000 { +>>>> + memory@00000000 { >>>> + device_type = "memory"; >>>> + reg = <0x0 0x00000000 0x0 0x80000000>; >>>> + }; @@ -162,14 +162,14 @@ On 2015/8/31 22:40, Leo Yan wrote: >>>> + }; >>>> + }; >>>> + ->>>> + cpu0: cpu at 20000 { +>>>> + cpu0: cpu@20000 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>> >>> Change to "arm,cortex-a57","arm,armv8"? >>> >> ->> Ok?but I think should be "hisilicon,hip05","arm,armv8". +>> Ok，but I think should be "hisilicon,hip05","arm,armv8". > > If the CPU is a starndard ARM core (such like CA53, CA57, etc), you > need directly use the CPU type which has been defined in: diff --git a/a/content_digest b/N2/content_digest index 701a4c3..2fb5c65 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,10 +3,26 @@ "ref\020150831131244.GB6194@leoy-linaro\0" "ref\055E45A46.7040805@huawei.com\0" "ref\020150831144019.GA22491@leoy-linaro\0" - "From\0dingtianhong@huawei.com (Ding Tianhong)\0" - "Subject\0[PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" + "From\0Ding Tianhong <dingtianhong@huawei.com>\0" + "Subject\0Re: [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" "Date\0Tue, 1 Sep 2015 09:14:12 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Leo Yan <leo.yan@linaro.org>\0" + "Cc\0<mark.rutland@arm.com>" + <devicetree@vger.kernel.org> + <pawel.moll@arm.com> + <ijc+devicetree@hellion.org.uk> + <marc.zyngier@arm.com> + <catalin.marinas@arm.com> + <will.deacon@arm.com> + <linux-kernel@vger.kernel.org> + <xuwei5@hisilicon.com> + <linuxarm@huawei.com> + <robh+dt@kernel.org> + <haojian.zhuang@linaro.org> + <galak@codeaurora.org> + <zhangfei.gao@linaro.org> + <rob.herring@linaro.org> + " <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "On 2015/8/31 22:40, Leo Yan wrote:\n" @@ -63,7 +79,7 @@ ">>>> +\tmodel = \"Hisilicon Hip05 D02 Development Board\";\n" ">>>> +\tcompatible = \"hisilicon,hip05-d02\";\n" ">>>> +\n" - ">>>> +\tmemory at 00000000 {\n" + ">>>> +\tmemory@00000000 {\n" ">>>> +\t\tdevice_type = \"memory\";\n" ">>>> +\t\treg = <0x0 0x00000000 0x0 0x80000000>;\n" ">>>> +\t};\n" @@ -173,14 +189,14 @@ ">>>> +\t\t\t};\n" ">>>> +\t\t};\n" ">>>> +\n" - ">>>> +\t\tcpu0: cpu at 20000 {\n" + ">>>> +\t\tcpu0: cpu@20000 {\n" ">>>> +\t\t\tdevice_type = \"cpu\";\n" ">>>> +\t\t\tcompatible = \"arm,armv8\";\n" ">>>\n" ">>> Change to \"arm,cortex-a57\",\"arm,armv8\"?\n" ">>>\n" ">>\n" - ">> Ok?but I think should be \"hisilicon,hip05\",\"arm,armv8\".\n" + ">> Ok\357\274\214but I think should be \"hisilicon,hip05\",\"arm,armv8\".\n" "> \n" "> If the CPU is a starndard ARM core (such like CA53, CA57, etc), you\n" "> need directly use the CPU type which has been defined in:\n" @@ -198,4 +214,4 @@ "> .\n" > -9cce0e5c6f9ac5768afbb27d02c7aa68863a3c84a1947957047feaa41e628af9 +bac629bcbc4ebe9834771c5b6e78a8ec90dbec511745ac96e5b8ace706a7e00c
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