Re: [PATCH] ASoC: Document DAI signal polarity

["arnaud.mouiche@invoxia.com" <arnaud.mouiche@invoxia.com>]

So, this example is a "normal" FSYNC, "normal" BCLK, DSP-B mode, 16 
bits/sample, isn't it (just to have something visual).
regards,
arnaud

--+  +--+  +--+  +--+  +--+  +--+  +--+  +--
   |  |  |  |  |  |  |  |  |  |  |  |  |  |    ...
   +--+  +--+  +--+  +--+  +--+  +--+  +--+

               +-----+
               |     |
--------------+     +------------------------ ...

   | b1  | b0  | b15 | b14 | b13 | b12 | b11 | ...

--frame N-1--> <----- frame N ---------


Le 31/08/2015 22:50, Anatol Pomozov a écrit :
> Per discussion at [1] currently there is no clear definition of what is FSYNC polarity.
> Different drivers use its own definition of what is "normal" and what is "inverted"
> fsync in different modes. This leads to compatibility problems between drivers.
>
> Explicitly specify meaning of BCLK/FSYNC polarity.
>
> [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2015-August/097121.html
>
> Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
> ---
>   include/sound/soc-dai.h | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
> index 2df96b1..c8170c4 100644
> --- a/include/sound/soc-dai.h
> +++ b/include/sound/soc-dai.h
> @@ -48,10 +48,15 @@ struct snd_compr_stream;
>   #define SND_SOC_DAIFMT_GATED		(0 << 4) /* clock is gated */
>   
>   /*
> - * DAI hardware signal inversions.
> + * DAI hardware signal polarity.
>    *
> - * Specifies whether the DAI can also support inverted clocks for the specified
> - * format.
> + * For BCLK:
> + *  - "normal" polarity means signal sensing happens at rising edge of BCLK
> + *  - "inverted" polarity means signal sensing happens at falling edge of BCLK
> + *
> + * For FSYNC:
> + *  - "normal" polarity means frame starts at rising edge of FSYNC
> + *  - "inverted" polarity means frame starts at falling edge of FSYNC
>    */
>   #define SND_SOC_DAIFMT_NB_NF		(0 << 8) /* normal bit clock + frame */
>   #define SND_SOC_DAIFMT_NB_IF		(2 << 8) /* normal BCLK + inv FRM */