From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWqHH-0007Yp-BK for qemu-devel@nongnu.org; Tue, 01 Sep 2015 14:27:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZWqHC-0003im-0J for qemu-devel@nongnu.org; Tue, 01 Sep 2015 14:27:27 -0400 Received: from mail-la0-x231.google.com ([2a00:1450:4010:c03::231]:34729) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWqHB-0003hj-Ns for qemu-devel@nongnu.org; Tue, 01 Sep 2015 14:27:21 -0400 Received: by laeb10 with SMTP id b10so5896488lae.1 for ; Tue, 01 Sep 2015 11:27:21 -0700 (PDT) References: <55E5DE06.2090207@gmail.com> From: "mar.krzeminski" Message-ID: <55E5EE06.8020804@gmail.com> Date: Tue, 1 Sep 2015 20:27:18 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] Adding secondary ARM processor List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: "qemu-devel@nongnu.org Developers" W dniu 01.09.2015 o 19:45, Peter Crosthwaite pisze: > On Tue, Sep 1, 2015 at 10:19 AM, mar.krzeminski > wrote: >> Hello, >> >> I have board with A9 processor (playing with vexpress model), >> for test I want to also add to this setup M3 processor. >> The problem is that secondary CPU sees the same device (eg. UART) with >> different address. > How far into the boot are you? Does A9 have MMU turned on? > > info mtree from the monitor should show the view of the address maps. > Anything weird there? I mess my question, sorry. I meant that address seen from M3 are different by design, eg. UART0 seen from M3 has base address 0x100, but same UART0 from A9 is mapped at 0x200 and I want to emulate this. This required some remapping at sysbus level (I think), and I do not know how to do that - even where to start, that is why I need your help. >> I can not figure out, how should I do that. Is it possible in qemu? > Yes it should be possible. > >> If yes, could you point me where I should start to look at it? >> > xlnx-zynqmp board, which does something similar with A53 and R5. It is > mixed with a combo of MMU and no-MMU capable CPUs. I saw this board, but my basic problem is with address mapping. > > Regards, > Peter > >> Regards, >> Marcin >>