From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Vrabel Subject: Re: xhci_hcd intterrupt affinity in Dom0/DomU limited to single interrupt Date: Wed, 2 Sep 2015 14:47:05 +0100 Message-ID: <55E6FDD9.1090301@citrix.com> References: <1441121643.26292.63.camel@citrix.com> <800613365.4285959.1441128848192.JavaMail.yahoo@mail.yahoo.com> <631331126.1156575.1441129186888.JavaMail.yahoo@mail.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <631331126.1156575.1441129186888.JavaMail.yahoo@mail.yahoo.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Justin Acker , "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org On 01/09/15 18:39, Justin Acker wrote: > Taking this to the dev list from users. > > Is there a way to force or enable pirq delivery to a set of cpus as > opposed to single device from being a assigned a single pirq so that its > interrupt can be distributed across multiple cpus? No. PIRQs are delivered via event channels and these can only be bound to one VCPU at a time. David