diff for duplicates of <55EBA945.3020501@huawei.com> diff --git a/a/1.txt b/N1/1.txt index b633723..d97b194 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -52,7 +52,7 @@ On 2015/9/5 17:28, Marc Zyngier wrote: >> + model = "Hisilicon Hip05 D02 Development Board"; >> + compatible = "hisilicon,hip05-d02"; >> + ->> + memory at 00000000 { +>> + memory@00000000 { >> + device_type = "memory"; >> + reg = <0x0 0x00000000 0x0 0x80000000>; >> + }; @@ -162,7 +162,7 @@ On 2015/9/5 17:28, Marc Zyngier wrote: >> + }; >> + }; >> + ->> + cpu0: cpu at 20000 { +>> + cpu0: cpu@20000 { >> + device_type = "cpu"; >> + compatible = "hisilicon,hip05", "arm,armv8"; > @@ -177,7 +177,7 @@ Ok. > [...] > ->> + gic: interrupt-controller at 8d000000 { +>> + gic: interrupt-controller@8d000000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; @@ -199,7 +199,7 @@ Yes, our chip need 192kb for GICR. >> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + ->> + its_totems: interrupt-controller at 8c000000 { +>> + its_totems: interrupt-controller@8c000000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + reg = <0x0 0x8c000000 0x0 0x1000000>; diff --git a/a/content_digest b/N1/content_digest index 7db099d..72b0dab 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,27 @@ "ref\01441421939-6236-1-git-send-email-dingtianhong@huawei.com\0" "ref\01441421939-6236-3-git-send-email-dingtianhong@huawei.com\0" "ref\020150905102807.18941767@arm.com\0" - "From\0dingtianhong@huawei.com (Ding Tianhong)\0" - "Subject\0[PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" + "From\0Ding Tianhong <dingtianhong@huawei.com>\0" + "Subject\0Re: [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" "Date\0Sun, 6 Sep 2015 10:47:33 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Marc Zyngier <marc.zyngier@arm.com>\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + linux-kernel@vger.kernel.org + catalin.marinas@arm.com + will.deacon@arm.com + devicetree@vger.kernel.org + robh+dt@kernel.org + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + rob.herring@linaro.org + haojian.zhuang@linaro.org + zhangfei.gao@linaro.org + xuwei5@hisilicon.com + leo.yan@linaro.org + zhizhou.zh@gmail.com + " linuxarm@huawei.com\0" "\00:1\0" "b\0" "On 2015/9/5 17:28, Marc Zyngier wrote:\n" @@ -61,7 +78,7 @@ ">> +\tmodel = \"Hisilicon Hip05 D02 Development Board\";\n" ">> +\tcompatible = \"hisilicon,hip05-d02\";\n" ">> +\n" - ">> +\tmemory at 00000000 {\n" + ">> +\tmemory@00000000 {\n" ">> +\t\tdevice_type = \"memory\";\n" ">> +\t\treg = <0x0 0x00000000 0x0 0x80000000>;\n" ">> +\t};\n" @@ -171,7 +188,7 @@ ">> +\t\t\t};\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu0: cpu at 20000 {\n" + ">> +\t\tcpu0: cpu@20000 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"hisilicon,hip05\", \"arm,armv8\";\n" "> \n" @@ -186,7 +203,7 @@ "\n" "> [...]\n" "> \n" - ">> +\tgic: interrupt-controller at 8d000000 {\n" + ">> +\tgic: interrupt-controller@8d000000 {\n" ">> +\t\tcompatible = \"arm,gic-v3\";\n" ">> + #interrupt-cells = <3>;\n" ">> + #address-cells = <2>;\n" @@ -208,7 +225,7 @@ ">> +\t\t <0x0 0xfe020000 0 0x10000>; /* GICV */\n" ">> +\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" ">> +\n" - ">> +\t\tits_totems: interrupt-controller at 8c000000 {\n" + ">> +\t\tits_totems: interrupt-controller@8c000000 {\n" ">> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" ">> +\t\t\tmsi-controller;\n" ">> +\t\t\treg = <0x0 0x8c000000 0x0 0x1000000>;\n" @@ -224,4 +241,4 @@ "> \tM.\n" > -8800be4d87f99b3eac87fe0285a3a28cd954a7baa6ba649a7fe4c2e4f86ad7ff +45fb6f5969b3e54ced6e08019cda7514c7a082470b552cf8abd964ebacf1cf46
diff --git a/a/1.txt b/N2/1.txt index b633723..d97b194 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -52,7 +52,7 @@ On 2015/9/5 17:28, Marc Zyngier wrote: >> + model = "Hisilicon Hip05 D02 Development Board"; >> + compatible = "hisilicon,hip05-d02"; >> + ->> + memory at 00000000 { +>> + memory@00000000 { >> + device_type = "memory"; >> + reg = <0x0 0x00000000 0x0 0x80000000>; >> + }; @@ -162,7 +162,7 @@ On 2015/9/5 17:28, Marc Zyngier wrote: >> + }; >> + }; >> + ->> + cpu0: cpu at 20000 { +>> + cpu0: cpu@20000 { >> + device_type = "cpu"; >> + compatible = "hisilicon,hip05", "arm,armv8"; > @@ -177,7 +177,7 @@ Ok. > [...] > ->> + gic: interrupt-controller at 8d000000 { +>> + gic: interrupt-controller@8d000000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; @@ -199,7 +199,7 @@ Yes, our chip need 192kb for GICR. >> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + ->> + its_totems: interrupt-controller at 8c000000 { +>> + its_totems: interrupt-controller@8c000000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + reg = <0x0 0x8c000000 0x0 0x1000000>; diff --git a/a/content_digest b/N2/content_digest index 7db099d..9b827ed 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,27 @@ "ref\01441421939-6236-1-git-send-email-dingtianhong@huawei.com\0" "ref\01441421939-6236-3-git-send-email-dingtianhong@huawei.com\0" "ref\020150905102807.18941767@arm.com\0" - "From\0dingtianhong@huawei.com (Ding Tianhong)\0" - "Subject\0[PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" + "From\0Ding Tianhong <dingtianhong@huawei.com>\0" + "Subject\0Re: [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board\0" "Date\0Sun, 6 Sep 2015 10:47:33 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Marc Zyngier <marc.zyngier@arm.com>\0" + "Cc\0<linux-arm-kernel@lists.infradead.org>" + <linux-kernel@vger.kernel.org> + <catalin.marinas@arm.com> + <will.deacon@arm.com> + <devicetree@vger.kernel.org> + <robh+dt@kernel.org> + <pawel.moll@arm.com> + <mark.rutland@arm.com> + <ijc+devicetree@hellion.org.uk> + <galak@codeaurora.org> + <rob.herring@linaro.org> + <haojian.zhuang@linaro.org> + <zhangfei.gao@linaro.org> + <xuwei5@hisilicon.com> + <leo.yan@linaro.org> + <zhizhou.zh@gmail.com> + " <linuxarm@huawei.com>\0" "\00:1\0" "b\0" "On 2015/9/5 17:28, Marc Zyngier wrote:\n" @@ -61,7 +78,7 @@ ">> +\tmodel = \"Hisilicon Hip05 D02 Development Board\";\n" ">> +\tcompatible = \"hisilicon,hip05-d02\";\n" ">> +\n" - ">> +\tmemory at 00000000 {\n" + ">> +\tmemory@00000000 {\n" ">> +\t\tdevice_type = \"memory\";\n" ">> +\t\treg = <0x0 0x00000000 0x0 0x80000000>;\n" ">> +\t};\n" @@ -171,7 +188,7 @@ ">> +\t\t\t};\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu0: cpu at 20000 {\n" + ">> +\t\tcpu0: cpu@20000 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"hisilicon,hip05\", \"arm,armv8\";\n" "> \n" @@ -186,7 +203,7 @@ "\n" "> [...]\n" "> \n" - ">> +\tgic: interrupt-controller at 8d000000 {\n" + ">> +\tgic: interrupt-controller@8d000000 {\n" ">> +\t\tcompatible = \"arm,gic-v3\";\n" ">> + #interrupt-cells = <3>;\n" ">> + #address-cells = <2>;\n" @@ -208,7 +225,7 @@ ">> +\t\t <0x0 0xfe020000 0 0x10000>; /* GICV */\n" ">> +\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" ">> +\n" - ">> +\t\tits_totems: interrupt-controller at 8c000000 {\n" + ">> +\t\tits_totems: interrupt-controller@8c000000 {\n" ">> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" ">> +\t\t\tmsi-controller;\n" ">> +\t\t\treg = <0x0 0x8c000000 0x0 0x1000000>;\n" @@ -224,4 +241,4 @@ "> \tM.\n" > -8800be4d87f99b3eac87fe0285a3a28cd954a7baa6ba649a7fe4c2e4f86ad7ff +4ed4d42dd74c0a655167ab90ab026149945d6577588ffd66b613eccf68fdd880
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