diff for duplicates of <55EF7803.2010004@kernel.org> diff --git a/a/1.txt b/N1/1.txt index adc81fe..09675b7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -35,7 +35,7 @@ Hardware designers either hate software folks or ensure our job security. >> So,I am planning to use the same compatible for L2 and L3, like this: >> >> ->> l2-cache at 500c0000 { +>> l2-cache@500c0000 { >> compatible = "socionext,uniphier-cache"; >> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, >> <0x506c0000 0x400>; @@ -51,7 +51,7 @@ Next level of the L2 is the L2? >> }; >> >> /* Not all of UniPhier SoCs have L3 cache */ ->> l3-cache at 500c8000 { +>> l3-cache@500c8000 { >> compatible = "socionext,uniphier-cache"; >> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, >> <0x506c8000 0x400>; diff --git a/a/content_digest b/N1/content_digest index a59804d..a2503fc 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,10 +3,31 @@ "ref\0CACRpkdbJppuA6ZyciNAGfSgrf4M2THVHggzuZYSqORjy2JBp_A@mail.gmail.com\0" "ref\0CAK7LNATWsa8AhyFGzsR0HAODmQD8yBPidTE0Lx2ACh4_PeQW9w@mail.gmail.com\0" "ref\0CACRpkdan0+rywnSR8Rs=aw63QAm3nN99ujqPcZwfpoh4_Dwc-w@mail.gmail.com\0" - "From\0robh@kernel.org (Rob Herring)\0" - "Subject\0[PATCH 1/3] ARM: uniphier: add outer cache support\0" + "From\0Rob Herring <robh@kernel.org>\0" + "Subject\0Re: [PATCH 1/3] ARM: uniphier: add outer cache support\0" "Date\0Tue, 8 Sep 2015 19:06:27 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Linus Walleij <linus.walleij@linaro.org>" + " Masahiro Yamada <yamada.masahiro@socionext.com>\0" + "Cc\0Mark Rutland <mark.rutland@arm.com>" + Jungseung Lee <js07.lee@gmail.com> + Florian Fainelli <f.fainelli@gmail.com> + Russell King <linux@arm.linux.org.uk> + Arnd Bergmann <arnd@arndb.de> + Mauro Carvalho Chehab <mchehab@osg.samsung.com> + arm@kernel.org <arm@kernel.org> + Jiri Slaby <jslaby@suse.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + Kees Cook <keescook@chromium.org> + Pawel Moll <pawel.moll@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + " Uwe Kleine-K\303\266nig <u.kleine-koenig@pengutronix.de>" + Joe Perches <joe@perches.com> + Rob Herring <robh+dt@kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + Paul Bolle <pebolle@tiscali.nl> + Greg KH <gregkh@linuxfoundation.org> + Nathan Lynch <nathan_lynch@mentor.com> + " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "On 09/08/2015 08:09 AM, Linus Walleij wrote:\n" @@ -46,7 +67,7 @@ ">> So,I am planning to use the same compatible for L2 and L3, like this:\n" ">>\n" ">>\n" - ">> l2-cache at 500c0000 {\n" + ">> l2-cache@500c0000 {\n" ">> compatible = \"socionext,uniphier-cache\";\n" ">> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,\n" ">> <0x506c0000 0x400>;\n" @@ -62,7 +83,7 @@ ">> };\n" ">>\n" ">> /* Not all of UniPhier SoCs have L3 cache */\n" - ">> l3-cache at 500c8000 {\n" + ">> l3-cache@500c8000 {\n" ">> compatible = \"socionext,uniphier-cache\";\n" ">> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,\n" ">> <0x506c8000 0x400>;\n" @@ -85,4 +106,4 @@ "\n" Rob -256bea8c440d661a580da23b5849ee8fc87625d68360f4cc9d24ae0521a5bb4d +3b067c6b43a66547d30cdc680db9e472756131a743745a6d4bd8c8b3b7b47538
diff --git a/a/1.txt b/N2/1.txt index adc81fe..09675b7 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -35,7 +35,7 @@ Hardware designers either hate software folks or ensure our job security. >> So,I am planning to use the same compatible for L2 and L3, like this: >> >> ->> l2-cache at 500c0000 { +>> l2-cache@500c0000 { >> compatible = "socionext,uniphier-cache"; >> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, >> <0x506c0000 0x400>; @@ -51,7 +51,7 @@ Next level of the L2 is the L2? >> }; >> >> /* Not all of UniPhier SoCs have L3 cache */ ->> l3-cache at 500c8000 { +>> l3-cache@500c8000 { >> compatible = "socionext,uniphier-cache"; >> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, >> <0x506c8000 0x400>; diff --git a/a/content_digest b/N2/content_digest index a59804d..524c2b8 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,10 +3,36 @@ "ref\0CACRpkdbJppuA6ZyciNAGfSgrf4M2THVHggzuZYSqORjy2JBp_A@mail.gmail.com\0" "ref\0CAK7LNATWsa8AhyFGzsR0HAODmQD8yBPidTE0Lx2ACh4_PeQW9w@mail.gmail.com\0" "ref\0CACRpkdan0+rywnSR8Rs=aw63QAm3nN99ujqPcZwfpoh4_Dwc-w@mail.gmail.com\0" - "From\0robh@kernel.org (Rob Herring)\0" - "Subject\0[PATCH 1/3] ARM: uniphier: add outer cache support\0" + "From\0Rob Herring <robh@kernel.org>\0" + "Subject\0Re: [PATCH 1/3] ARM: uniphier: add outer cache support\0" "Date\0Tue, 8 Sep 2015 19:06:27 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Linus Walleij <linus.walleij@linaro.org>" + " Masahiro Yamada <yamada.masahiro@socionext.com>\0" + "Cc\0Mark Rutland <mark.rutland@arm.com>" + Jungseung Lee <js07.lee@gmail.com> + Florian Fainelli <f.fainelli@gmail.com> + Russell King <linux@arm.linux.org.uk> + Arnd Bergmann <arnd@arndb.de> + Mauro Carvalho Chehab <mchehab@osg.samsung.com> + arm@kernel.org <arm@kernel.org> + Jiri Slaby <jslaby@suse.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + Kees Cook <keescook@chromium.org> + Pawel Moll <pawel.moll@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + " Uwe Kleine-K\303\266nig <u.kleine-koenig@pengutronix.de>" + Joe Perches <joe@perches.com> + Rob Herring <robh+dt@kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + Paul Bolle <pebolle@tiscali.nl> + Greg KH <gregkh@linuxfoundation.org> + Nathan Lynch <nathan_lynch@mentor.com> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + Maxime Coquelin <mcoquelin.stm32@gmail.com> + Kumar Gala <galak@codeaurora.org> + Tejun Heo <tj@kernel.org> + Andrew Morton <akpm@linux-foundation.org> + " David S. Miller <davem@davemloft.net>\0" "\00:1\0" "b\0" "On 09/08/2015 08:09 AM, Linus Walleij wrote:\n" @@ -46,7 +72,7 @@ ">> So,I am planning to use the same compatible for L2 and L3, like this:\n" ">>\n" ">>\n" - ">> l2-cache at 500c0000 {\n" + ">> l2-cache@500c0000 {\n" ">> compatible = \"socionext,uniphier-cache\";\n" ">> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,\n" ">> <0x506c0000 0x400>;\n" @@ -62,7 +88,7 @@ ">> };\n" ">>\n" ">> /* Not all of UniPhier SoCs have L3 cache */\n" - ">> l3-cache at 500c8000 {\n" + ">> l3-cache@500c8000 {\n" ">> compatible = \"socionext,uniphier-cache\";\n" ">> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,\n" ">> <0x506c8000 0x400>;\n" @@ -85,4 +111,4 @@ "\n" Rob -256bea8c440d661a580da23b5849ee8fc87625d68360f4cc9d24ae0521a5bb4d +53c11acc184a869a933a50cfbf46dd2ae5bd0fff7c03ff084806dca0a485f067
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