* [RESEND PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC @ 2015-09-10 6:11 ` Chen Feng 0 siblings, 0 replies; 11+ messages in thread From: Chen Feng @ 2015-09-10 6:11 UTC (permalink / raw) To: puck.chen, p.zabel, linux-kernel Cc: dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Add reset controller for hi6220 hikey-board. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3f03380..09bb9d1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -167,5 +167,12 @@ clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; clock-names = "uartclk", "apb_pclk"; }; + + reset_ctrl: reset_ctrl@f7030304 { + compatible = "hisilicon,hisi_reset_ctl"; + reg = <0x0 0xf7030304 0x0 0x1000>; + #reset-cells = <1>; + }; + }; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RESEND PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC @ 2015-09-10 6:11 ` Chen Feng 0 siblings, 0 replies; 11+ messages in thread From: Chen Feng @ 2015-09-10 6:11 UTC (permalink / raw) To: puck.chen, p.zabel, linux-kernel Cc: dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Add reset controller for hi6220 hikey-board. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3f03380..09bb9d1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -167,5 +167,12 @@ clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; clock-names = "uartclk", "apb_pclk"; }; + + reset_ctrl: reset_ctrl@f7030304 { + compatible = "hisilicon,hisi_reset_ctl"; + reg = <0x0 0xf7030304 0x0 0x1000>; + #reset-cells = <1>; + }; + }; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RESEND PATCH 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings 2015-09-10 6:11 ` Chen Feng @ 2015-09-10 6:11 ` Chen Feng -1 siblings, 0 replies; 11+ messages in thread From: Chen Feng @ 2015-09-10 6:11 UTC (permalink / raw) To: puck.chen, p.zabel, linux-kernel Cc: dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Add DT bindings documentation for hi6220 SoC reset controller. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> --- .../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +- 2 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt new file mode 100644 index 0000000..8a23f50 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -0,0 +1,97 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller node must be a sub-node of the chip controller +node on SoCs. + +Required properties: +- compatible: may be "hisilicon,hisi_reset_ctl" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +Example: + + reset_ctrl: reset_ctrl@f7030304 { + compatible = "hisilicon,hi6220_reset_ctl"; + reg = <0x0 0xf7030304 0x0 0x1000>; + #reset-cells = <1>; + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + uart1: uart1@..... { + ... + resets = <&reset_ctrl 0x305>; + ... + }; + +The following RESET_INDEX values are valid for hi6220 SoC: + PERIPH_RSTDIS0_MMC0 = 0x000, + PERIPH_RSTDIS0_MMC1 = 0x001, + PERIPH_RSTDIS0_MMC2 = 0x002, + PERIPH_RSTDIS0_NANDC = 0x003, + PERIPH_RSTDIS0_USBOTG_BUS = 0x004, + PERIPH_RSTDIS0_POR_PICOPHY = 0x005, + PERIPH_RSTDIS0_USBOTG = 0x006, + PERIPH_RSTDIS0_USBOTG_32K = 0x007, + + PERIPH_RSTDIS1_HIFI = 0x100, + PERIPH_RSTDIS1_DIGACODEC = 0x105, + + PERIPH_RSTEN2_IPF = 0x200, + PERIPH_RSTEN2_SOCP = 0x201, + PERIPH_RSTEN2_DMAC = 0x202, + PERIPH_RSTEN2_SECENG = 0x203, + PERIPH_RSTEN2_ABB = 0x204, + PERIPH_RSTEN2_HPM0 = 0x205, + PERIPH_RSTEN2_HPM1 = 0x206, + PERIPH_RSTEN2_HPM2 = 0x207, + PERIPH_RSTEN2_HPM3 = 0x208, + + PERIPH_RSTEN3_CSSYS = 0x300, + PERIPH_RSTEN3_I2C0 = 0x301, + PERIPH_RSTEN3_I2C1 = 0x302, + PERIPH_RSTEN3_I2C2 = 0x303, + PERIPH_RSTEN3_I2C3 = 0x304, + PERIPH_RSTEN3_UART1 = 0x305, + PERIPH_RSTEN3_UART2 = 0x306, + PERIPH_RSTEN3_UART3 = 0x307, + PERIPH_RSTEN3_UART4 = 0x308, + PERIPH_RSTEN3_SSP = 0x309, + PERIPH_RSTEN3_PWM = 0x30a, + PERIPH_RSTEN3_BLPWM = 0x30b, + PERIPH_RSTEN3_TSENSOR = 0x30c, + PERIPH_RSTEN3_DAPB = 0x312, + PERIPH_RSTEN3_HKADC = 0x313, + PERIPH_RSTEN3_CODEC_SSI = 0x314, + PERIPH_RSTEN3_PMUSSI1 = 0x316, + + PERIPH_RSTEN8_RS0 = 0x400, + PERIPH_RSTEN8_RS2 = 0x401, + PERIPH_RSTEN8_RS3 = 0x402, + PERIPH_RSTEN8_MS0 = 0x403, + PERIPH_RSTEN8_MS2 = 0x405, + PERIPH_RSTEN8_XG2RAM0 = 0x406, + PERIPH_RSTEN8_X2SRAM_TZMA = 0x407, + PERIPH_RSTEN8_SRAM = 0x408, + PERIPH_RSTEN8_HARQ = 0x40a, + PERIPH_RSTEN8_DDRC = 0x40c, + PERIPH_RSTEN8_DDRC_APB = 0x40d, + PERIPH_RSTEN8_DDRPACK_APB = 0x40e, + PERIPH_RSTEN8_DDRT = 0x411, + + PERIPH_RSDIST9_CARM_DAP = 0x500, + PERIPH_RSDIST9_CARM_ATB = 0x501, + PERIPH_RSDIST9_CARM_LBUS = 0x502, + PERIPH_RSDIST9_CARM_POR = 0x503, + PERIPH_RSDIST9_CARM_CORE = 0x504, + PERIPH_RSDIST9_CARM_DBG = 0x505, + PERIPH_RSDIST9_CARM_L2 = 0x506, + PERIPH_RSDIST9_CARM_SOCDBG = 0x507, + PERIPH_RSDIST9_CARM_ETM = 0x508, diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 09bb9d1..111537a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -169,7 +169,7 @@ }; reset_ctrl: reset_ctrl@f7030304 { - compatible = "hisilicon,hisi_reset_ctl"; + compatible = "hisilicon,hi6220_reset_ctl"; reg = <0x0 0xf7030304 0x0 0x1000>; #reset-cells = <1>; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RESEND PATCH 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings @ 2015-09-10 6:11 ` Chen Feng 0 siblings, 0 replies; 11+ messages in thread From: Chen Feng @ 2015-09-10 6:11 UTC (permalink / raw) To: puck.chen, p.zabel, linux-kernel Cc: dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Add DT bindings documentation for hi6220 SoC reset controller. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> --- .../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +- 2 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt new file mode 100644 index 0000000..8a23f50 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -0,0 +1,97 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller node must be a sub-node of the chip controller +node on SoCs. + +Required properties: +- compatible: may be "hisilicon,hisi_reset_ctl" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +Example: + + reset_ctrl: reset_ctrl@f7030304 { + compatible = "hisilicon,hi6220_reset_ctl"; + reg = <0x0 0xf7030304 0x0 0x1000>; + #reset-cells = <1>; + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + uart1: uart1@..... { + ... + resets = <&reset_ctrl 0x305>; + ... + }; + +The following RESET_INDEX values are valid for hi6220 SoC: + PERIPH_RSTDIS0_MMC0 = 0x000, + PERIPH_RSTDIS0_MMC1 = 0x001, + PERIPH_RSTDIS0_MMC2 = 0x002, + PERIPH_RSTDIS0_NANDC = 0x003, + PERIPH_RSTDIS0_USBOTG_BUS = 0x004, + PERIPH_RSTDIS0_POR_PICOPHY = 0x005, + PERIPH_RSTDIS0_USBOTG = 0x006, + PERIPH_RSTDIS0_USBOTG_32K = 0x007, + + PERIPH_RSTDIS1_HIFI = 0x100, + PERIPH_RSTDIS1_DIGACODEC = 0x105, + + PERIPH_RSTEN2_IPF = 0x200, + PERIPH_RSTEN2_SOCP = 0x201, + PERIPH_RSTEN2_DMAC = 0x202, + PERIPH_RSTEN2_SECENG = 0x203, + PERIPH_RSTEN2_ABB = 0x204, + PERIPH_RSTEN2_HPM0 = 0x205, + PERIPH_RSTEN2_HPM1 = 0x206, + PERIPH_RSTEN2_HPM2 = 0x207, + PERIPH_RSTEN2_HPM3 = 0x208, + + PERIPH_RSTEN3_CSSYS = 0x300, + PERIPH_RSTEN3_I2C0 = 0x301, + PERIPH_RSTEN3_I2C1 = 0x302, + PERIPH_RSTEN3_I2C2 = 0x303, + PERIPH_RSTEN3_I2C3 = 0x304, + PERIPH_RSTEN3_UART1 = 0x305, + PERIPH_RSTEN3_UART2 = 0x306, + PERIPH_RSTEN3_UART3 = 0x307, + PERIPH_RSTEN3_UART4 = 0x308, + PERIPH_RSTEN3_SSP = 0x309, + PERIPH_RSTEN3_PWM = 0x30a, + PERIPH_RSTEN3_BLPWM = 0x30b, + PERIPH_RSTEN3_TSENSOR = 0x30c, + PERIPH_RSTEN3_DAPB = 0x312, + PERIPH_RSTEN3_HKADC = 0x313, + PERIPH_RSTEN3_CODEC_SSI = 0x314, + PERIPH_RSTEN3_PMUSSI1 = 0x316, + + PERIPH_RSTEN8_RS0 = 0x400, + PERIPH_RSTEN8_RS2 = 0x401, + PERIPH_RSTEN8_RS3 = 0x402, + PERIPH_RSTEN8_MS0 = 0x403, + PERIPH_RSTEN8_MS2 = 0x405, + PERIPH_RSTEN8_XG2RAM0 = 0x406, + PERIPH_RSTEN8_X2SRAM_TZMA = 0x407, + PERIPH_RSTEN8_SRAM = 0x408, + PERIPH_RSTEN8_HARQ = 0x40a, + PERIPH_RSTEN8_DDRC = 0x40c, + PERIPH_RSTEN8_DDRC_APB = 0x40d, + PERIPH_RSTEN8_DDRPACK_APB = 0x40e, + PERIPH_RSTEN8_DDRT = 0x411, + + PERIPH_RSDIST9_CARM_DAP = 0x500, + PERIPH_RSDIST9_CARM_ATB = 0x501, + PERIPH_RSDIST9_CARM_LBUS = 0x502, + PERIPH_RSDIST9_CARM_POR = 0x503, + PERIPH_RSDIST9_CARM_CORE = 0x504, + PERIPH_RSDIST9_CARM_DBG = 0x505, + PERIPH_RSDIST9_CARM_L2 = 0x506, + PERIPH_RSDIST9_CARM_SOCDBG = 0x507, + PERIPH_RSDIST9_CARM_ETM = 0x508, diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 09bb9d1..111537a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -169,7 +169,7 @@ }; reset_ctrl: reset_ctrl@f7030304 { - compatible = "hisilicon,hisi_reset_ctl"; + compatible = "hisilicon,hi6220_reset_ctl"; reg = <0x0 0xf7030304 0x0 0x1000>; #reset-cells = <1>; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [RESEND PATCH 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings 2015-09-10 6:11 ` Chen Feng (?) @ 2015-09-10 9:40 ` Philipp Zabel -1 siblings, 0 replies; 11+ messages in thread From: Philipp Zabel @ 2015-09-10 9:40 UTC (permalink / raw) To: Chen Feng Cc: linux-kernel, dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Am Donnerstag, den 10.09.2015, 14:11 +0800 schrieb Chen Feng: > Add DT bindings documentation for hi6220 SoC reset controller. > > Signed-off-by: Chen Feng <puck.chen@hisilicon.com> > --- > .../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +- > 2 files changed, 98 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt > > diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt > new file mode 100644 > index 0000000..8a23f50 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt > @@ -0,0 +1,97 @@ > +Hisilicon System Reset Controller > +====================================== > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +The reset controller node must be a sub-node of the chip controller > +node on SoCs. > + > +Required properties: > +- compatible: may be "hisilicon,hisi_reset_ctl" > +- reg: should be register base and length as documented in the > + datasheet > +- #reset-cells: 1, see below > + > +Example: > + > + reset_ctrl: reset_ctrl@f7030304 { > + compatible = "hisilicon,hi6220_reset_ctl"; See my comments for patch 1. Also, is this called reset_ctrl or reset_ctl in the data sheets? > + reg = <0x0 0xf7030304 0x0 0x1000>; > + #reset-cells = <1>; > + }; > + > +Specifying reset lines connected to IP modules > +============================================== > +example: > + > + uart1: uart1@..... { > + ... > + resets = <&reset_ctrl 0x305>; > + ... > + }; > + > +The following RESET_INDEX values are valid for hi6220 SoC: > + PERIPH_RSTDIS0_MMC0 = 0x000, > + PERIPH_RSTDIS0_MMC1 = 0x001, > + PERIPH_RSTDIS0_MMC2 = 0x002, > + PERIPH_RSTDIS0_NANDC = 0x003, > + PERIPH_RSTDIS0_USBOTG_BUS = 0x004, > + PERIPH_RSTDIS0_POR_PICOPHY = 0x005, > + PERIPH_RSTDIS0_USBOTG = 0x006, > + PERIPH_RSTDIS0_USBOTG_32K = 0x007, > + > + PERIPH_RSTDIS1_HIFI = 0x100, > + PERIPH_RSTDIS1_DIGACODEC = 0x105, > + > + PERIPH_RSTEN2_IPF = 0x200, > + PERIPH_RSTEN2_SOCP = 0x201, > + PERIPH_RSTEN2_DMAC = 0x202, > + PERIPH_RSTEN2_SECENG = 0x203, > + PERIPH_RSTEN2_ABB = 0x204, > + PERIPH_RSTEN2_HPM0 = 0x205, > + PERIPH_RSTEN2_HPM1 = 0x206, > + PERIPH_RSTEN2_HPM2 = 0x207, > + PERIPH_RSTEN2_HPM3 = 0x208, > + > + PERIPH_RSTEN3_CSSYS = 0x300, > + PERIPH_RSTEN3_I2C0 = 0x301, > + PERIPH_RSTEN3_I2C1 = 0x302, > + PERIPH_RSTEN3_I2C2 = 0x303, > + PERIPH_RSTEN3_I2C3 = 0x304, > + PERIPH_RSTEN3_UART1 = 0x305, > + PERIPH_RSTEN3_UART2 = 0x306, > + PERIPH_RSTEN3_UART3 = 0x307, > + PERIPH_RSTEN3_UART4 = 0x308, > + PERIPH_RSTEN3_SSP = 0x309, > + PERIPH_RSTEN3_PWM = 0x30a, > + PERIPH_RSTEN3_BLPWM = 0x30b, > + PERIPH_RSTEN3_TSENSOR = 0x30c, > + PERIPH_RSTEN3_DAPB = 0x312, > + PERIPH_RSTEN3_HKADC = 0x313, > + PERIPH_RSTEN3_CODEC_SSI = 0x314, > + PERIPH_RSTEN3_PMUSSI1 = 0x316, > + > + PERIPH_RSTEN8_RS0 = 0x400, > + PERIPH_RSTEN8_RS2 = 0x401, > + PERIPH_RSTEN8_RS3 = 0x402, > + PERIPH_RSTEN8_MS0 = 0x403, > + PERIPH_RSTEN8_MS2 = 0x405, > + PERIPH_RSTEN8_XG2RAM0 = 0x406, > + PERIPH_RSTEN8_X2SRAM_TZMA = 0x407, > + PERIPH_RSTEN8_SRAM = 0x408, > + PERIPH_RSTEN8_HARQ = 0x40a, > + PERIPH_RSTEN8_DDRC = 0x40c, > + PERIPH_RSTEN8_DDRC_APB = 0x40d, > + PERIPH_RSTEN8_DDRPACK_APB = 0x40e, > + PERIPH_RSTEN8_DDRT = 0x411, > + > + PERIPH_RSDIST9_CARM_DAP = 0x500, > + PERIPH_RSDIST9_CARM_ATB = 0x501, > + PERIPH_RSDIST9_CARM_LBUS = 0x502, > + PERIPH_RSDIST9_CARM_POR = 0x503, > + PERIPH_RSDIST9_CARM_CORE = 0x504, > + PERIPH_RSDIST9_CARM_DBG = 0x505, > + PERIPH_RSDIST9_CARM_L2 = 0x506, > + PERIPH_RSDIST9_CARM_SOCDBG = 0x507, > + PERIPH_RSDIST9_CARM_ETM = 0x508, > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > index 09bb9d1..111537a 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > @@ -169,7 +169,7 @@ > }; > > reset_ctrl: reset_ctrl@f7030304 { > - compatible = "hisilicon,hisi_reset_ctl"; > + compatible = "hisilicon,hi6220_reset_ctl"; > reg = <0x0 0xf7030304 0x0 0x1000>; > #reset-cells = <1>; > }; Please drop this change from this patch, fix patch 1 instead. regards Philipp ^ permalink raw reply [flat|nested] 11+ messages in thread
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* [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC 2015-09-10 6:11 ` Chen Feng @ 2015-09-10 6:11 ` Chen Feng -1 siblings, 0 replies; 11+ messages in thread From: Chen Feng @ 2015-09-10 6:11 UTC (permalink / raw) To: puck.chen-C8/M+/jPZTeaMJb+Lgu22Q, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q, w.f-hv44wF8Li93QT0dZR+AlfA, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A, bintian.wang-hv44wF8Li93QT0dZR+AlfA, devicetree-u79uwXL29TY76Z2rM5mHXA Add reset driver for hi6220-hikey board,this driver supply deassert of IP. on hi6220 SoC. Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> --- drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/hisilicon/Kconfig | 5 +++ drivers/reset/hisilicon/Makefile | 1 + drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+) create mode 100644 drivers/reset/hisilicon/Kconfig create mode 100644 drivers/reset/hisilicon/Makefile create mode 100644 drivers/reset/hisilicon/hi6220_reset.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 0615f50..df37212 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER If unsure, say no. source "drivers/reset/sti/Kconfig" +source "drivers/reset/hisilicon/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..331d7b2 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_HISI) += hisilicon/ diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig new file mode 100644 index 0000000..bceed14 --- /dev/null +++ b/drivers/reset/hisilicon/Kconfig @@ -0,0 +1,5 @@ +config COMMON_RESET_HI6220 + tristate "Hi6220 Clock Driver" + depends on (ARCH_HISI && RESET_CONTROLLER) + help + Build the Hisilicon Hi6220 reset driver. diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile new file mode 100644 index 0000000..c932f86 --- /dev/null +++ b/drivers/reset/hisilicon/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c new file mode 100644 index 0000000..a88fc57 --- /dev/null +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -0,0 +1,74 @@ +/* + * Hisilicon Hi6220 reset controller driver + * + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Feng Chen <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/reset-controller.h> +#include <linux/reset.h> + +static void __iomem *src_base; +static DEFINE_SPINLOCK(reset_lock); + +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + unsigned long timeout; + unsigned long flags; + int bit; + u32 val; + + int bank = idx >> 8; + int offset = idx & 0xff; + + spin_lock_irqsave(&reset_lock, flags); + + val = readl(src_base + (bank * 0x10)); + writel(val | BIT(offset), src_base + (bank * 0x10)); + + spin_unlock_irqrestore(&reset_lock, flags); + + return 0; + +} + +static struct reset_control_ops hi6220_reset_ops = { + .deassert = hi6220_reset_module, +}; + +static struct reset_controller_dev hi6220_reset_dev = { + .ops = &hi6220_reset_ops, + .nr_resets = 0xffff, +}; + +static void __init hi6220_reset_init(void) +{ + struct device_node *np; + struct reset_control *test = NULL; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); + if (!np) { + pr_err("find reset node in dts error!\n"); + return; + } + src_base = of_iomap(np, 0); + WARN_ON(!src_base); + + hi6220_reset_dev.of_node = np; + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) + reset_controller_register(&hi6220_reset_dev); +} + +postcore_initcall(hi6220_reset_init); + -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC @ 2015-09-10 6:11 ` Chen Feng 0 siblings, 0 replies; 11+ messages in thread From: Chen Feng @ 2015-09-10 6:11 UTC (permalink / raw) To: puck.chen, p.zabel, linux-kernel Cc: dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Add reset driver for hi6220-hikey board,this driver supply deassert of IP. on hi6220 SoC. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> --- drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/hisilicon/Kconfig | 5 +++ drivers/reset/hisilicon/Makefile | 1 + drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+) create mode 100644 drivers/reset/hisilicon/Kconfig create mode 100644 drivers/reset/hisilicon/Makefile create mode 100644 drivers/reset/hisilicon/hi6220_reset.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 0615f50..df37212 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER If unsure, say no. source "drivers/reset/sti/Kconfig" +source "drivers/reset/hisilicon/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..331d7b2 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_HISI) += hisilicon/ diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig new file mode 100644 index 0000000..bceed14 --- /dev/null +++ b/drivers/reset/hisilicon/Kconfig @@ -0,0 +1,5 @@ +config COMMON_RESET_HI6220 + tristate "Hi6220 Clock Driver" + depends on (ARCH_HISI && RESET_CONTROLLER) + help + Build the Hisilicon Hi6220 reset driver. diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile new file mode 100644 index 0000000..c932f86 --- /dev/null +++ b/drivers/reset/hisilicon/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c new file mode 100644 index 0000000..a88fc57 --- /dev/null +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -0,0 +1,74 @@ +/* + * Hisilicon Hi6220 reset controller driver + * + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Feng Chen <puck.chen@hisilicon.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/reset-controller.h> +#include <linux/reset.h> + +static void __iomem *src_base; +static DEFINE_SPINLOCK(reset_lock); + +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + unsigned long timeout; + unsigned long flags; + int bit; + u32 val; + + int bank = idx >> 8; + int offset = idx & 0xff; + + spin_lock_irqsave(&reset_lock, flags); + + val = readl(src_base + (bank * 0x10)); + writel(val | BIT(offset), src_base + (bank * 0x10)); + + spin_unlock_irqrestore(&reset_lock, flags); + + return 0; + +} + +static struct reset_control_ops hi6220_reset_ops = { + .deassert = hi6220_reset_module, +}; + +static struct reset_controller_dev hi6220_reset_dev = { + .ops = &hi6220_reset_ops, + .nr_resets = 0xffff, +}; + +static void __init hi6220_reset_init(void) +{ + struct device_node *np; + struct reset_control *test = NULL; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); + if (!np) { + pr_err("find reset node in dts error!\n"); + return; + } + src_base = of_iomap(np, 0); + WARN_ON(!src_base); + + hi6220_reset_dev.of_node = np; + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) + reset_controller_register(&hi6220_reset_dev); +} + +postcore_initcall(hi6220_reset_init); + -- 1.9.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC 2015-09-10 6:11 ` Chen Feng (?) @ 2015-09-10 9:40 ` Philipp Zabel 2015-09-10 10:49 ` chenfeng -1 siblings, 1 reply; 11+ messages in thread From: Philipp Zabel @ 2015-09-10 9:40 UTC (permalink / raw) To: Chen Feng Cc: linux-kernel, dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Am Donnerstag, den 10.09.2015, 14:11 +0800 schrieb Chen Feng: > Add reset driver for hi6220-hikey board,this driver supply deassert > of IP. on hi6220 SoC. > > Signed-off-by: Chen Feng <puck.chen@hisilicon.com> > --- > drivers/reset/Kconfig | 1 + > drivers/reset/Makefile | 1 + > drivers/reset/hisilicon/Kconfig | 5 +++ > drivers/reset/hisilicon/Makefile | 1 + > drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ > 5 files changed, 82 insertions(+) > create mode 100644 drivers/reset/hisilicon/Kconfig > create mode 100644 drivers/reset/hisilicon/Makefile > create mode 100644 drivers/reset/hisilicon/hi6220_reset.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 0615f50..df37212 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER > If unsure, say no. > > source "drivers/reset/sti/Kconfig" > +source "drivers/reset/hisilicon/Kconfig" > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..331d7b2 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > +obj-$(CONFIG_ARCH_HISI) += hisilicon/ > diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig > new file mode 100644 > index 0000000..bceed14 > --- /dev/null > +++ b/drivers/reset/hisilicon/Kconfig > @@ -0,0 +1,5 @@ > +config COMMON_RESET_HI6220 > + tristate "Hi6220 Clock Driver" "Clock"? Should probably be "Reset". > + depends on (ARCH_HISI && RESET_CONTROLLER) > + help > + Build the Hisilicon Hi6220 reset driver. > diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile > new file mode 100644 > index 0000000..c932f86 > --- /dev/null > +++ b/drivers/reset/hisilicon/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o > diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c > new file mode 100644 > index 0000000..a88fc57 > --- /dev/null > +++ b/drivers/reset/hisilicon/hi6220_reset.c > @@ -0,0 +1,74 @@ > +/* > + * Hisilicon Hi6220 reset controller driver > + * > + * Copyright (c) 2015 Hisilicon Limited. > + * > + * Author: Feng Chen <puck.chen@hisilicon.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/init.h> > +#include <linux/bitops.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/reset-controller.h> > +#include <linux/reset.h> > + > +static void __iomem *src_base; > +static DEFINE_SPINLOCK(reset_lock); > + > +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, > + unsigned long idx) > +{ > + unsigned long timeout; > + unsigned long flags; > + int bit; > + u32 val; > + > + int bank = idx >> 8; > + int offset = idx & 0xff; > + > + spin_lock_irqsave(&reset_lock, flags); > + > + val = readl(src_base + (bank * 0x10)); > + writel(val | BIT(offset), src_base + (bank * 0x10)); Are these registers write-once, otherwise any reason not to implement reset_assert, too? > + spin_unlock_irqrestore(&reset_lock, flags); > + > + return 0; > + > +} > + > +static struct reset_control_ops hi6220_reset_ops = { > + .deassert = hi6220_reset_module, > +}; > + > +static struct reset_controller_dev hi6220_reset_dev = { > + .ops = &hi6220_reset_ops, > + .nr_resets = 0xffff, This can't be correct, you only have 4 KiB register space. > +}; > + > +static void __init hi6220_reset_init(void) > +{ > + struct device_node *np; > + struct reset_control *test = NULL; > + > + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); Better use "hisilicon,hi6220-reset-ctl" instead. > + if (!np) { > + pr_err("find reset node in dts error!\n"); > + return; > + } > + src_base = of_iomap(np, 0); > + WARN_ON(!src_base); > + > + hi6220_reset_dev.of_node = np; > + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) > + reset_controller_register(&hi6220_reset_dev); > +} > + > +postcore_initcall(hi6220_reset_init); > + Drop this empty line. best regards Philipp ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC 2015-09-10 9:40 ` Philipp Zabel @ 2015-09-10 10:49 ` chenfeng 0 siblings, 0 replies; 11+ messages in thread From: chenfeng @ 2015-09-10 10:49 UTC (permalink / raw) To: Philipp Zabel Cc: linux-kernel, dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Zabel, Thanks for review. On 2015/9/10 17:40, Philipp Zabel wrote: > Am Donnerstag, den 10.09.2015, 14:11 +0800 schrieb Chen Feng: >> Add reset driver for hi6220-hikey board,this driver supply deassert >> of IP. on hi6220 SoC. >> >> Signed-off-by: Chen Feng <puck.chen@hisilicon.com> >> --- >> drivers/reset/Kconfig | 1 + >> drivers/reset/Makefile | 1 + >> drivers/reset/hisilicon/Kconfig | 5 +++ >> drivers/reset/hisilicon/Makefile | 1 + >> drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ >> 5 files changed, 82 insertions(+) >> create mode 100644 drivers/reset/hisilicon/Kconfig >> create mode 100644 drivers/reset/hisilicon/Makefile >> create mode 100644 drivers/reset/hisilicon/hi6220_reset.c >> >> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig >> index 0615f50..df37212 100644 >> --- a/drivers/reset/Kconfig >> +++ b/drivers/reset/Kconfig >> @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER >> If unsure, say no. >> >> source "drivers/reset/sti/Kconfig" >> +source "drivers/reset/hisilicon/Kconfig" >> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile >> index 157d421..331d7b2 100644 >> --- a/drivers/reset/Makefile >> +++ b/drivers/reset/Makefile >> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o >> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o >> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o >> obj-$(CONFIG_ARCH_STI) += sti/ >> +obj-$(CONFIG_ARCH_HISI) += hisilicon/ >> diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig >> new file mode 100644 >> index 0000000..bceed14 >> --- /dev/null >> +++ b/drivers/reset/hisilicon/Kconfig >> @@ -0,0 +1,5 @@ >> +config COMMON_RESET_HI6220 >> + tristate "Hi6220 Clock Driver" > > "Clock"? Should probably be "Reset". > >> + depends on (ARCH_HISI && RESET_CONTROLLER) >> + help >> + Build the Hisilicon Hi6220 reset driver. >> diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile >> new file mode 100644 >> index 0000000..c932f86 >> --- /dev/null >> +++ b/drivers/reset/hisilicon/Makefile >> @@ -0,0 +1 @@ >> +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o >> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c >> new file mode 100644 >> index 0000000..a88fc57 >> --- /dev/null >> +++ b/drivers/reset/hisilicon/hi6220_reset.c >> @@ -0,0 +1,74 @@ >> +/* >> + * Hisilicon Hi6220 reset controller driver >> + * >> + * Copyright (c) 2015 Hisilicon Limited. >> + * >> + * Author: Feng Chen <puck.chen@hisilicon.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ >> + >> +#include <linux/init.h> >> +#include <linux/bitops.h> >> +#include <linux/io.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/reset-controller.h> >> +#include <linux/reset.h> >> + >> +static void __iomem *src_base; >> +static DEFINE_SPINLOCK(reset_lock); >> + >> +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, >> + unsigned long idx) >> +{ >> + unsigned long timeout; >> + unsigned long flags; >> + int bit; >> + u32 val; >> + >> + int bank = idx >> 8; >> + int offset = idx & 0xff; >> + >> + spin_lock_irqsave(&reset_lock, flags); >> + >> + val = readl(src_base + (bank * 0x10)); >> + writel(val | BIT(offset), src_base + (bank * 0x10)); > > Are these registers write-once, otherwise any reason not to implement > reset_assert, too? > >> + spin_unlock_irqrestore(&reset_lock, flags); >> + >> + return 0; >> + >> +} >> + >> +static struct reset_control_ops hi6220_reset_ops = { >> + .deassert = hi6220_reset_module, >> +}; >> + >> +static struct reset_controller_dev hi6220_reset_dev = { >> + .ops = &hi6220_reset_ops, >> + .nr_resets = 0xffff, > > This can't be correct, you only have 4 KiB register space. > >> +}; >> + >> +static void __init hi6220_reset_init(void) >> +{ >> + struct device_node *np; >> + struct reset_control *test = NULL; >> + >> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); > > Better use "hisilicon,hi6220-reset-ctl" instead. > Totally agree! >> + if (!np) { >> + pr_err("find reset node in dts error!\n"); >> + return; >> + } >> + src_base = of_iomap(np, 0); >> + WARN_ON(!src_base); >> + >> + hi6220_reset_dev.of_node = np; >> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) >> + reset_controller_register(&hi6220_reset_dev); >> +} >> + >> +postcore_initcall(hi6220_reset_init); >> + > > Drop this empty line. > > best regards > Philipp > > > . > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC @ 2015-09-10 10:49 ` chenfeng 0 siblings, 0 replies; 11+ messages in thread From: chenfeng @ 2015-09-10 10:49 UTC (permalink / raw) To: Philipp Zabel Cc: linux-kernel, dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Zabel, Thanks for review. On 2015/9/10 17:40, Philipp Zabel wrote: > Am Donnerstag, den 10.09.2015, 14:11 +0800 schrieb Chen Feng: >> Add reset driver for hi6220-hikey board,this driver supply deassert >> of IP. on hi6220 SoC. >> >> Signed-off-by: Chen Feng <puck.chen@hisilicon.com> >> --- >> drivers/reset/Kconfig | 1 + >> drivers/reset/Makefile | 1 + >> drivers/reset/hisilicon/Kconfig | 5 +++ >> drivers/reset/hisilicon/Makefile | 1 + >> drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ >> 5 files changed, 82 insertions(+) >> create mode 100644 drivers/reset/hisilicon/Kconfig >> create mode 100644 drivers/reset/hisilicon/Makefile >> create mode 100644 drivers/reset/hisilicon/hi6220_reset.c >> >> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig >> index 0615f50..df37212 100644 >> --- a/drivers/reset/Kconfig >> +++ b/drivers/reset/Kconfig >> @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER >> If unsure, say no. >> >> source "drivers/reset/sti/Kconfig" >> +source "drivers/reset/hisilicon/Kconfig" >> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile >> index 157d421..331d7b2 100644 >> --- a/drivers/reset/Makefile >> +++ b/drivers/reset/Makefile >> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o >> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o >> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o >> obj-$(CONFIG_ARCH_STI) += sti/ >> +obj-$(CONFIG_ARCH_HISI) += hisilicon/ >> diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig >> new file mode 100644 >> index 0000000..bceed14 >> --- /dev/null >> +++ b/drivers/reset/hisilicon/Kconfig >> @@ -0,0 +1,5 @@ >> +config COMMON_RESET_HI6220 >> + tristate "Hi6220 Clock Driver" > > "Clock"? Should probably be "Reset". > >> + depends on (ARCH_HISI && RESET_CONTROLLER) >> + help >> + Build the Hisilicon Hi6220 reset driver. >> diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile >> new file mode 100644 >> index 0000000..c932f86 >> --- /dev/null >> +++ b/drivers/reset/hisilicon/Makefile >> @@ -0,0 +1 @@ >> +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o >> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c >> new file mode 100644 >> index 0000000..a88fc57 >> --- /dev/null >> +++ b/drivers/reset/hisilicon/hi6220_reset.c >> @@ -0,0 +1,74 @@ >> +/* >> + * Hisilicon Hi6220 reset controller driver >> + * >> + * Copyright (c) 2015 Hisilicon Limited. >> + * >> + * Author: Feng Chen <puck.chen@hisilicon.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ >> + >> +#include <linux/init.h> >> +#include <linux/bitops.h> >> +#include <linux/io.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/reset-controller.h> >> +#include <linux/reset.h> >> + >> +static void __iomem *src_base; >> +static DEFINE_SPINLOCK(reset_lock); >> + >> +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, >> + unsigned long idx) >> +{ >> + unsigned long timeout; >> + unsigned long flags; >> + int bit; >> + u32 val; >> + >> + int bank = idx >> 8; >> + int offset = idx & 0xff; >> + >> + spin_lock_irqsave(&reset_lock, flags); >> + >> + val = readl(src_base + (bank * 0x10)); >> + writel(val | BIT(offset), src_base + (bank * 0x10)); > > Are these registers write-once, otherwise any reason not to implement > reset_assert, too? > >> + spin_unlock_irqrestore(&reset_lock, flags); >> + >> + return 0; >> + >> +} >> + >> +static struct reset_control_ops hi6220_reset_ops = { >> + .deassert = hi6220_reset_module, >> +}; >> + >> +static struct reset_controller_dev hi6220_reset_dev = { >> + .ops = &hi6220_reset_ops, >> + .nr_resets = 0xffff, > > This can't be correct, you only have 4 KiB register space. > >> +}; >> + >> +static void __init hi6220_reset_init(void) >> +{ >> + struct device_node *np; >> + struct reset_control *test = NULL; >> + >> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); > > Better use "hisilicon,hi6220-reset-ctl" instead. > Totally agree! >> + if (!np) { >> + pr_err("find reset node in dts error!\n"); >> + return; >> + } >> + src_base = of_iomap(np, 0); >> + WARN_ON(!src_base); >> + >> + hi6220_reset_dev.of_node = np; >> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) >> + reset_controller_register(&hi6220_reset_dev); >> +} >> + >> +postcore_initcall(hi6220_reset_init); >> + > > Drop this empty line. > > best regards > Philipp > > > . > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RESEND PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC 2015-09-10 6:11 ` Chen Feng ` (2 preceding siblings ...) (?) @ 2015-09-10 9:38 ` Philipp Zabel -1 siblings, 0 replies; 11+ messages in thread From: Philipp Zabel @ 2015-09-10 9:38 UTC (permalink / raw) To: Chen Feng Cc: linux-kernel, dan.zhao, w.f, haojian.zhuang, bintian.wang, devicetree Hi, Am Donnerstag, den 10.09.2015, 14:11 +0800 schrieb Chen Feng: > Add reset controller for hi6220 hikey-board. > > Signed-off-by: Chen Feng <puck.chen@hisilicon.com> > --- > arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > index 3f03380..09bb9d1 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > @@ -167,5 +167,12 @@ > clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; > clock-names = "uartclk", "apb_pclk"; > }; > + > + reset_ctrl: reset_ctrl@f7030304 { > + compatible = "hisilicon,hisi_reset_ctl"; Please use hyphens instead of underscores here, also in the next patch you modify the compatible value. I suggest to use compatible = "hisilicon,hi6220-reset-ctl"; here. regards Philipp ^ permalink raw reply [flat|nested] 11+ messages in thread
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2015-09-10 6:11 [RESEND PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
2015-09-10 6:11 ` Chen Feng
2015-09-10 6:11 ` [RESEND PATCH 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-09-10 6:11 ` Chen Feng
2015-09-10 9:40 ` Philipp Zabel
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2015-09-10 6:11 ` [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
2015-09-10 6:11 ` Chen Feng
2015-09-10 9:40 ` Philipp Zabel
2015-09-10 10:49 ` chenfeng
2015-09-10 10:49 ` chenfeng
2015-09-10 9:38 ` [RESEND PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Philipp Zabel
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