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From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] nios2: remap and translate reg address in device tree
Date: Mon, 14 Sep 2015 07:39:13 +0200	[thread overview]
Message-ID: <55F65D81.7040604@denx.de> (raw)
In-Reply-To: <1442133130-11174-1-git-send-email-thomas@wytron.com.tw>

Hi Thomas,

added Simon and Stephen to cc on this.

On 13.09.2015 10:32, Thomas Chou wrote:
> As the io space remapping ioremap() and bridge address
> translation fdt_translate_address() are not usually used
> in u-boot driver model by dev_get_addr(). We would better
> convert the reg address map in the device tree of nios2
> boards, so that it is io mapped and bridge translated.

So you are changing the DT sources for your platform because the U-Boot 
implementation does support the bus translation correctly (ranges 
properties)? I think this is the wrong approach. We need to make sure 
that U-Boot supports DT correctly instead. I have a patch queued to 
enable this. Please take a look at this thread:

https://patchwork.ozlabs.org/patch/514331/

Could you please check if this patch (with the config options enabled) 
helps on your platform without DT changes?

> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
> ---
>   arch/nios2/dts/3c120_devboard.dts | 171 +++++++++++++++-----------------------
>   1 file changed, 69 insertions(+), 102 deletions(-)
>
> diff --git a/arch/nios2/dts/3c120_devboard.dts b/arch/nios2/dts/3c120_devboard.dts
> index 02524ab..70d71a5 100644
> --- a/arch/nios2/dts/3c120_devboard.dts
> +++ b/arch/nios2/dts/3c120_devboard.dts
> @@ -14,6 +14,73 @@
>   	#address-cells = <1>;
>   	#size-cells = <1>;
>
> +	aliases {
> +		console = &jtag_uart;
> +	};
> +
> +	timer_1ms: timer at 0x400000 {
> +		compatible = "altr,timer-1.0";
> +		reg = <0xe8400000 0x00000020>;
> +		interrupt-parent = <&cpu>;
> +		interrupts = <11>;
> +		clock-frequency = <125000000>;
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	jtag_uart: serial at 0x4d50 {
> +		compatible = "altr,juart-1.0";
> +		reg = <0xe8004d50 0x00000008>;
> +		interrupt-parent = <&cpu>;
> +		interrupts = <1>;
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	tse_mac: ethernet at 0x4000 {
> +		compatible = "altr,tse-1.0";
> +		reg = <0xe8004000 0x00000400>,
> +			<0xe8004400 0x00000040>,
> +			<0xe8004800 0x00000040>,
> +			<0xe8002000 0x00002000>;
> +		reg-names = "control_port", "rx_csr", "tx_csr", "s1";
> +		interrupt-parent = <&cpu>;
> +		interrupts = <2 3>;
> +		interrupt-names = "rx_irq", "tx_irq";
> +		rx-fifo-depth = <8192>;
> +		tx-fifo-depth = <8192>;
> +		max-frame-size = <1518>;
> +		local-mac-address = [ 00 00 00 00 00 00 ];
> +		phy-mode = "rgmii-id";
> +		phy-handle = <&phy0>;
> +		tse_mac_mdio: mdio {
> +			compatible = "altr,tse-mdio";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			phy0: ethernet-phy at 18 {
> +				reg = <18>;
> +				device_type = "ethernet-phy";
> +			};
> +		};
> +	};
> +
> +	uart: serial at 0x4c80 {
> +		compatible = "altr,uart-1.0";
> +		reg = <0xe8004c80 0x00000020>;
> +		interrupt-parent = <&cpu>;
> +		interrupts = <10>;
> +		current-speed = <115200>;
> +		clock-frequency = <62500000>;
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	user_led_pio_8out: gpio at 0x4cc0 {
> +		compatible = "altr,pio-1.0";
> +		reg = <0xe8004cc0 0x00000010>;
> +		resetvalue = <255>;
> +		width = <8>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +	};
> +
>   	cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
> @@ -46,108 +113,8 @@
>
>   	memory at 0 {
>   		device_type = "memory";
> -		reg = <0x10000000 0x08000000>,
> -			<0x07fff400 0x00000400>;
> +		reg = <0xd0000000 0x08000000>,
> +			<0xc7fff400 0x00000400>;
>   	};
>
> -	sopc at 0 {
> -		device_type = "soc";
> -		ranges;
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		compatible = "altr,avalon", "simple-bus";
> -		bus-frequency = <125000000>;
> -
> -		pb_cpu_to_io: bridge at 0x8000000 {
> -			compatible = "simple-bus";
> -			reg = <0x08000000 0x00800000>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges = <0x00002000 0x08002000 0x00002000>,
> -				<0x00004000 0x08004000 0x00000400>,
> -				<0x00004400 0x08004400 0x00000040>,
> -				<0x00004800 0x08004800 0x00000040>,
> -				<0x00004c80 0x08004c80 0x00000020>,
> -				<0x00004d50 0x08004d50 0x00000008>,
> -				<0x00008000 0x08008000 0x00000020>,
> -				<0x00400000 0x08400000 0x00000020>;
> -
> -			timer_1ms: timer at 0x400000 {
> -				compatible = "altr,timer-1.0";
> -				reg = <0x00400000 0x00000020>;
> -				interrupt-parent = <&cpu>;
> -				interrupts = <11>;
> -				clock-frequency = <125000000>;
> -			};
> -
> -			timer_0: timer at 0x8000 {
> -				compatible = "altr,timer-1.0";
> -				reg = < 0x00008000 0x00000020 >;
> -				interrupt-parent = < &cpu >;
> -				interrupts = < 5 >;
> -				clock-frequency = < 125000000 >;
> -			};
> -
> -			jtag_uart: serial at 0x4d50 {
> -				compatible = "altr,juart-1.0";
> -				reg = <0x00004d50 0x00000008>;
> -				interrupt-parent = <&cpu>;
> -				interrupts = <1>;
> -			};
> -
> -			tse_mac: ethernet at 0x4000 {
> -				compatible = "altr,tse-1.0";
> -				reg = <0x00004000 0x00000400>,
> -					<0x00004400 0x00000040>,
> -					<0x00004800 0x00000040>,
> -					<0x00002000 0x00002000>;
> -				reg-names = "control_port", "rx_csr", "tx_csr", "s1";
> -				interrupt-parent = <&cpu>;
> -				interrupts = <2 3>;
> -				interrupt-names = "rx_irq", "tx_irq";
> -				rx-fifo-depth = <8192>;
> -				tx-fifo-depth = <8192>;
> -				max-frame-size = <1518>;
> -				local-mac-address = [ 00 00 00 00 00 00 ];
> -				phy-mode = "rgmii-id";
> -				phy-handle = <&phy0>;
> -				tse_mac_mdio: mdio {
> -					compatible = "altr,tse-mdio";
> -					#address-cells = <1>;
> -					#size-cells = <0>;
> -					phy0: ethernet-phy at 18 {
> -						reg = <18>;
> -						device_type = "ethernet-phy";
> -					};
> -				};
> -			};
> -
> -			uart: serial at 0x4c80 {
> -				compatible = "altr,uart-1.0";
> -				reg = <0x00004c80 0x00000020>;
> -				interrupt-parent = <&cpu>;
> -				interrupts = <10>;
> -				current-speed = <115200>;
> -				clock-frequency = <62500000>;
> -			};
> -		};
> -
> -		cfi_flash_64m: flash at 0x0 {
> -			compatible = "cfi-flash";
> -			reg = <0x00000000 0x04000000>;
> -			bank-width = <2>;
> -			device-width = <1>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -
> -			partition at 800000 {
> -				reg = <0x00800000 0x01e00000>;
> -				label = "JFFS2 Filesystem";
> -			};
> -		};
> -	};
> -
> -	chosen {
> -		bootargs = "debug console=ttyJ0,115200";
> -	};
>   };
>

Thanks,
Stefan

  parent reply	other threads:[~2015-09-14  5:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-13  8:32 [U-Boot] [PATCH 1/2] nios2: remap and translate reg address in device tree Thomas Chou
2015-09-13  8:32 ` [U-Boot] [PATCH 2/2] nios2: convert altera_jtag_uart to driver model Thomas Chou
2015-09-13 13:42   ` Marek Vasut
2015-09-13 13:39 ` [U-Boot] [PATCH 1/2] nios2: remap and translate reg address in device tree Marek Vasut
2015-09-14 12:39   ` Simon Glass
2015-09-15  4:48   ` Thomas Chou
2015-09-13 13:40 ` [U-Boot] [PATCH v2 0/3] nios2: convert altera_jtag_uart to driver model Thomas Chou
2015-09-13 13:40   ` [U-Boot] [PATCH v2 1/3] nios2: map physical address to uncached virtual address Thomas Chou
2015-09-13 13:46     ` Marek Vasut
2015-10-01 22:49       ` Simon Glass
2015-10-02  0:16         ` Thomas Chou
2015-10-02 11:21           ` Simon Glass
2015-09-13 13:40   ` [U-Boot] [PATCH v2 2/3] nios2: remove bridges in device tree Thomas Chou
2015-09-13 13:40   ` [U-Boot] [PATCH v2 3/3] nios2: convert altera_jtag_uart to driver model Thomas Chou
2015-09-14  5:39 ` Stefan Roese [this message]
2015-09-15  0:50   ` [U-Boot] [PATCH 1/2] nios2: remap and translate reg address in device tree Thomas Chou

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