From mboxrd@z Thu Jan 1 00:00:00 1970 From: f.fainelli@gmail.com (Florian Fainelli) Date: Fri, 18 Sep 2015 12:22:56 -0700 Subject: [PATCH v2 2/3] soc: brcmstb: Add Bus Interface Unit control setup In-Reply-To: <1442340900-15320-3-git-send-email-f.fainelli@gmail.com> References: <1442340900-15320-1-git-send-email-f.fainelli@gmail.com> <1442340900-15320-3-git-send-email-f.fainelli@gmail.com> Message-ID: <55FC6490.7000204@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 15/09/15 11:14, Florian Fainelli wrote: > Broadcom STB SoCs (brcmstb) require an early setup of their Bus > Interface Unit control register, this needs to happen before SMP is > brought up because it affects how the CPU complex will be interfaced to > the memory controller. > > Add support code which properly initializes the BIU registers based on > whether "brcm,write-pairing" is present in Device Tree, and take care of > saving and restoring credit register settings during system-wide > suspend/resume operations. > > Signed-off-by: Florian Fainelli Applied to soc/next with Gregory's tag and the revised function prototype returning void. -- Florian From mboxrd@z Thu Jan 1 00:00:00 1970 From: Florian Fainelli Subject: Re: [PATCH v2 2/3] soc: brcmstb: Add Bus Interface Unit control setup Date: Fri, 18 Sep 2015 12:22:56 -0700 Message-ID: <55FC6490.7000204@gmail.com> References: <1442340900-15320-1-git-send-email-f.fainelli@gmail.com> <1442340900-15320-3-git-send-email-f.fainelli@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1442340900-15320-3-git-send-email-f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Florian Fainelli , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, gregory.0xf0-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org List-Id: devicetree@vger.kernel.org On 15/09/15 11:14, Florian Fainelli wrote: > Broadcom STB SoCs (brcmstb) require an early setup of their Bus > Interface Unit control register, this needs to happen before SMP is > brought up because it affects how the CPU complex will be interfaced to > the memory controller. > > Add support code which properly initializes the BIU registers based on > whether "brcm,write-pairing" is present in Device Tree, and take care of > saving and restoring credit register settings during system-wide > suspend/resume operations. > > Signed-off-by: Florian Fainelli Applied to soc/next with Gregory's tag and the revised function prototype returning void. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html