From mboxrd@z Thu Jan 1 00:00:00 1970 From: Martin Peres Subject: Re: PWM-based voltage management input clock Date: Sat, 19 Sep 2015 19:21:04 +0300 Message-ID: <55FD8B70.6010704@free.fr> References: <55FC7081.7050007@free.fr> <20150918203051.GA23395@prokofiev.nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20150918203051.GA23395-FqhoBIChHNk6p33qAC56yVaTQe2KTcn/@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: Andy Ritger Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, gpu-public-documentation List-Id: nouveau.vger.kernel.org T24gMTgvMDkvMTUgMjM6MzAsIEFuZHkgUml0Z2VyIHdyb3RlOgo+IFRoYW5rcywgTWFydGluLiAg SSdsbCB0cnkgdG8gZm9sbG93IHVwIG9uIHRoaXMgbmV4dCB3ZWVrIGFuZCBnZXQgeW91IGFuIGFu c3dlci4gIFdoYXQgR1BVcyBoYXZlIHlvdSBvYnNlcnZlZCB0aGlzIG9uPwo+ClRoYW5rcyBBbmR5 LAoKQXMgZmFyIGFzIEkgY2FuIHRlbGwsIGl0IGlzIHRoZSBjYXNlIGZvciBhbGwgR1BVcyB1c2lu ZyB0aGUgUFdNLWJhc2VkIAp2b2x0YWdlIG1hbmFnZW1lbnQuIFRvIGJlIG1vcmUgc3BlY2lmaWMs IHdlIGhhdmUgc2VlbiB0aGlzIGJlaGF2aW91ciBvbiAKYSBHSzEwNiAobW9iaWxlKSwgYSBHTTEx NyBhbmQgYSBHTTIwNC4KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KTm91dmVhdSBtYWlsaW5nIGxpc3QKTm91dmVhdUBsaXN0cy5mcmVlZGVza3RvcC5vcmcK aHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL25vdXZlYXUK