From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 1/2] xen: arm: traps: check hsr.ec for ARM32 Date: Mon, 21 Sep 2015 10:47:23 +0100 Message-ID: <55FFD22B.4090601@citrix.com> References: <1442819224-25390-1-git-send-email-Peng.Fan@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1442819224-25390-1-git-send-email-Peng.Fan@freescale.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Peng Fan , xen-devel@lists.xen.org Cc: Stefano Stabellini , Ian Campbell List-Id: xen-devel@lists.xenproject.org Hi Peng, On 21/09/15 08:07, Peng Fan wrote: > To ARM64, "if ( hsr.ec >= 0x10 ) return 1;" is ok for unconditional > check, but to ARM32, we need to use 'hsr.ec >> 30' to check. hsr.ec is encoded on 5 bits, therefore the shift you suggest is wrong. Maybe you wanted to use (hsr.ec >> 4)? Although, can you explain why you need a different check for ARM32? Regards, > Signed-off-by: Peng Fan > Cc: Ian Campbell > Cc: Stefano Stabellini > Cc: Julien Grall > --- > xen/arch/arm/traps.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index 9d2bd6a..2e2b1f2 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -1531,8 +1531,13 @@ static int check_conditional_instr(struct cpu_user_regs *regs, > int cond; > > /* Unconditional Exception classes */ > +#ifdef CONFIG_ARM_64 > if ( hsr.ec >= 0x10 ) > return 1; > +#else > + if ( hsr.ec >> 30 ) > + return 1; > +#endif > > /* Check for valid condition in hsr */ > cond = hsr.cond.ccvalid ? hsr.cond.cc : -1; > -- Julien Grall