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From: Yu Dai <yu.dai@intel.com>
To: Sagar Arun Kamble <sagar.a.kamble@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: Akash Goel <akash.goel@intel.com>
Subject: Re: [PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count
Date: Mon, 21 Sep 2015 11:50:23 -0700	[thread overview]
Message-ID: <5600516F.1030809@intel.com> (raw)
In-Reply-To: <1442033276-2191-6-git-send-email-sagar.a.kamble@intel.com>

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> Cc: Alex Dai <yu.dai@intel.com>
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c     | 4 ++++
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 8c8e574..9d79a6b 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -53,6 +53,7 @@
>   #define   START_DMA			  (1<<0)
>   #define DMA_GUC_WOPCM_OFFSET		0xc340
>   #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
> +#define GUC_MAX_IDLE_COUNT		0xC3E4
>   
>   #define GUC_WOPCM_SIZE			0xc050
>   #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4d6bb6b..6843a48 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4841,6 +4841,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>   	for_each_ring(ring, dev_priv, unused)
>   		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +
> +	if (HAS_GUC_UCODE(dev))
> +		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> +
>   	I915_WRITE(GEN6_RC_SLEEP, 0);
>   	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>   

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  reply	other threads:[~2015-09-21 21:00 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-12  4:47 [PATCH v2 0/7] Gen9 RC6, Turbo, Coarse Power Gating Fixes Sagar Arun Kamble
2015-09-12  4:47 ` [PATCH v2 1/7] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
2015-09-21 18:49   ` Yu Dai
2015-09-12  4:47 ` [PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:49   ` Yu Dai
2015-09-23  8:49   ` Daniel Vetter
2015-09-12  4:47 ` [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode Sagar Arun Kamble
2015-09-21 18:49   ` Yu Dai
2015-09-21 21:47     ` O'Rourke, Tom
2015-09-23  8:50   ` Daniel Vetter
2015-09-23  9:33     ` Kamble, Sagar A
2015-09-23  9:36     ` [PATCH 1/1] drm/i915: Update Promotion timer for RC6 TO Mode Sagar Arun Kamble
2015-09-24 21:11       ` O'Rourke, Tom
2015-09-30 10:43         ` [PATCH v2 " Sagar Arun Kamble
2015-09-30 16:38           ` O'Rourke, Tom
2015-10-01  8:21           ` Daniel Vetter
2015-09-12  4:47 ` [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:50   ` Yu Dai
2015-09-23  8:51   ` Daniel Vetter
2015-09-12  4:47 ` [PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count Sagar Arun Kamble
2015-09-21 18:50   ` Yu Dai [this message]
2015-09-12  4:47 ` [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly Sagar Arun Kamble
2015-09-21 16:51   ` Yu Dai
2015-09-22 22:51     ` Yu Dai
2015-09-21 18:59   ` Yu Dai
2015-09-12  4:47 ` [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
2015-09-21 11:24   ` [PATCH v3 1/1] " Sagar Arun Kamble
2015-09-21 18:50   ` [PATCH v2 7/7] " Yu Dai
2015-09-23  6:32     ` Kamble, Sagar A
2015-09-23  8:53     ` Daniel Vetter

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